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4df539c0c5
The cn9130.dtsi defines a pinctrl node for SPI1 (until recently it was mislabeled as spi0). Use this instead of having a duplicate definition with a different label. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
252 lines
4.7 KiB
Text
252 lines
4.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Marvell International Ltd.
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*/
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#include "cn9130.dtsi" /* include SoC device tree */
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/ {
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model = "CN9130-CRB";
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compatible = "marvell,cn9130-crb",
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"marvell,cn9130",
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"marvell,armada-ap806-quad",
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"marvell,armada-ap806";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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i2c0 = &cp0_i2c0;
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spi0 = &cp0_spi1;
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gpio0 = &ap_gpio0;
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gpio1 = &cp0_gpio0;
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gpio2 = &cp0_gpio1;
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};
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memory@00000000 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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cp0 {
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config-space {
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sdhci@780000 {
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vqmmc-supply = <&cp0_reg_sd_vccq>;
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vmmc-supply = <&cp0_reg_sd_vcc>;
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};
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cp0_reg_sd_vccq: cp0_sd_vccq@0 {
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compatible = "regulator-gpio";
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regulator-name = "cp0_sd_vccq";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&cp0_gpio1 18 GPIO_ACTIVE_HIGH>;
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states = <1800000 0x1
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3300000 0x0>;
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};
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cp0_reg_sd_vcc: cp0_sd_vcc@0 {
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compatible = "regulator-fixed";
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regulator-name = "cp0_sd_vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&cp0_gpio1 22 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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/*
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* AP related configuration
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*/
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&ap_pinctl {
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/* MPP Bus:
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* SDIO [0-10, 12]
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* UART0 [11,19]
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 1 1 1 1 1 1 1 1 1 1
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1 3 1 0 0 0 0 0 0 3 >;
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};
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/* on-board eMMC - U6 */
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&ap_sdhci0 {
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pinctrl-names = "default";
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pinctrl-0 = <&ap_emmc_pins>;
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bus-width = <8>;
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status = "okay";
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};
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/*
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* CP related configuration
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*/
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&cp0_pinctl {
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/* MPP Bus:
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* [0-11] RGMII1
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* [12] GPIO
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* [13-16] SPI1
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* [17-32] GPIO
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* [33] SD_PWR_OFF
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* [34] CP_PCIE0_CLKREQn
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* [35-38] I2C1 I2C0
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* [39] GPIO
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* [40-43] SMI/XSMI
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* [44-46] GPIO
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* [47] UART1_TX
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* [48] GPIO
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* [49] SD_HST_18_EN
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* [50] GPIO
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* [51] SD_PWR_0
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* [52] PCIE_RSTn
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* [53] UART1_RX
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* [54] GPIO
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* [55] SD_DT
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* [56-61] SDIO
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*
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* Note that CRB board revisions have different MPP configurations.
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* r1p2 has SPI flash on MPP[30:27] and r1p3.1, which is the latest
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* board revision, has it mapped to MPP[16:13].
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 3 3 3 3 3 3 3 3 3 3
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3 3 0 3 3 3 3 0 0 0
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0 0 0 0 0 0 0 0 0 0
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0 0 0 6 9 2 2 2 2 0
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8 8 8 8 0 0 0 7 0 0xa
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0 0xa 9 7 0 0xb 0xe 0xe 0xe 0xe
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0xe 0xe 0xe>;
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cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
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marvell,pins = < 55 >;
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marvell,function = <0>;
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};
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cp0_smi_pins_crb: cp0-smi-pins-crb {
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marvell,pins = < 40 41 >;
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marvell,function = <8>;
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};
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cp0_xsmi_pins_crb: cp0-xsmi-pins-crb {
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marvell,pins = < 42 43 >;
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marvell,function = <8>;
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};
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};
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/*
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* CP0
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*/
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&cp0_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c0_pins>;
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status = "okay";
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clock-frequency = <100000>;
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};
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&cp0_i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c1_pins>;
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status = "okay";
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};
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&cp0_sdhci0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_sdhci_pins
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&cp0_sdhci_cd_pins_crb>;
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bus-width = <4>;
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vqmmc-supply = <&cp0_reg_sd_vccq>;
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vmmc-supply = <&cp0_reg_sd_vcc>;
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status = "okay";
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};
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&cp0_spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_spi1_pins>;
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reg = <0x700680 0x50>, /* control */
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<0x2000000 0x1000000>, /* CS0 */
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<0 0xffffffff>, /* CS1 */
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<0 0xffffffff>, /* CS2 */
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<0 0xffffffff>; /* CS3 */
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status = "okay";
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spi-flash@0 {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "jedec,spi-nor", "spi-flash";
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reg = <0x0>;
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/* On-board MUX does not allow higher frequencies */
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spi-max-frequency = <40000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0x0 0x200000>;
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};
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partition@400000 {
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label = "Filesystem";
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reg = <0x200000 0xe00000>;
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};
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};
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};
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};
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&cp0_utmi0 {
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status = "okay";
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};
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&cp0_utmi1 {
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status = "okay";
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};
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&cp0_mdio {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_smi_pins_crb>;
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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switch6: ethernet-switch@6 {
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reg = <6>;
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};
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};
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&cp0_xmdio {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_xsmi_pins_crb>;
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status = "okay";
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nbaset_phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&cp0_ethernet {
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status = "okay";
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};
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&cp0_eth0 {
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status = "okay";
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phy-mode = "sfi";
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};
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&cp0_eth1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_ge1_rgmii_pins>;
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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&cp0_eth2 {
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/* Disable it for now, as mainline does not support this IF yet */
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status = "disabled";
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phy = <&nbaset_phy0>;
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};
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