mirror of
https://github.com/AsahiLinux/u-boot
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e7fb789612
OF_HOSTFILE is used on sandbox configs only. Although it's pretty unique and not causing any confusions, we are better of having simpler config options for the DTB. So let's replace that with the existing OF_BOARD. U-Boot would then have only three config options for the DTB origin. - OF_SEPARATE, build separately from U-Boot - OF_BOARD, board specific way of providing the DTB - OF_EMBED embedded in the u-boot binary(should not be used in production Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
168 lines
3.4 KiB
C
168 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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* Sharma Bhupesh <bhupesh.sharma@freescale.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <init.h>
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#include <malloc.h>
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#include <errno.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <linux/compiler.h>
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#include <dm/platform_data/serial_pl01x.h>
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#include "pcie.h"
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#include <asm/armv8/mmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const struct pl01x_serial_plat serial_plat = {
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.base = V2M_UART0,
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.type = TYPE_PL011,
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.clock = CONFIG_PL011_CLOCK,
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};
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U_BOOT_DRVINFO(vexpress_serials) = {
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.name = "serial_pl01x",
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.plat = &serial_plat,
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};
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static struct mm_region vexpress64_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0xff80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = vexpress64_mem_map;
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/* This function gets replaced by platforms supporting PCIe.
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* The replacement function, eg. on Juno, initialises the PCIe bus.
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*/
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__weak void vexpress64_pcie_init(void)
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{
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}
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int board_init(void)
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{
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vexpress64_pcie_init();
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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#ifdef PHYS_SDRAM_2
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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#endif
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return 0;
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}
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#ifdef CONFIG_OF_BOARD
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#define JUNO_FLASH_SEC_SIZE (256 * 1024)
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static phys_addr_t find_dtb_in_nor_flash(const char *partname)
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{
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phys_addr_t sector = CONFIG_SYS_FLASH_BASE;
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int i;
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for (i = 0;
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i < CONFIG_SYS_MAX_FLASH_SECT;
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i++, sector += JUNO_FLASH_SEC_SIZE) {
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int len = strlen(partname) + 1;
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int offs;
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phys_addr_t imginfo;
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u32 reg;
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reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x04);
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/* This makes up the string "HSLFTOOF" flash footer */
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if (reg != 0x464F4F54U)
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continue;
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reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x08);
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if (reg != 0x464C5348U)
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continue;
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for (offs = 0; offs < 32; offs += 4, len -= 4) {
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reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x30 + offs);
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if (strncmp(partname + offs, (char *)®,
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len > 4 ? 4 : len))
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break;
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if (len > 4)
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continue;
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reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x10);
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imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg;
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reg = readl(imginfo + 0x54);
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return CONFIG_SYS_FLASH_BASE +
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reg * JUNO_FLASH_SEC_SIZE;
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}
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}
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printf("No DTB found\n");
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return ~0;
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}
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void *board_fdt_blob_setup(int *err)
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{
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phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART);
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*err = 0;
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if (fdt_rom_addr == ~0UL) {
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*err = -ENXIO;
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return NULL;
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}
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return (void *)fdt_rom_addr;
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}
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#endif
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/* Actual reset is done via PSCI. */
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void reset_cpu(void)
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{
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}
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/*
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* Board specific ethernet initialization routine.
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*/
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int board_eth_init(struct bd_info *bis)
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{
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int rc = 0;
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#ifndef CONFIG_DM_ETH
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#ifdef CONFIG_SMC91111
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rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
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#endif
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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#endif
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return rc;
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}
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