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14177e47e8
This patch adds the basic clocks support for the Allwinner A31 (sun6i)
processor. This code will not been compiled until the build is hooked
up in a later patch. It has been split out to keep the patches manageable.
This includes changes from the following commits from u-boot-sunxi:
a92051b ARM: sunxi: Add sun6i clock controller structure
1f72c6f ARM: sun6i: Setup the UART0 clocks
5f2e712 ARM: sunxi: Enable pll6 by default on all models
2be2f2a ARM: sunxi-mmc: Add mmc support for sun6i / A31
12e1633 ARM: sun6i: Add initial clock setup for SPL
1a9c9c6 ARM: sunxi: Split clock code into common, sun4i and sun6i code
0b194ee ARM: sun6i: Properly setup the PLL LDO in clock_init_safe
b54c626 sunxi: avoid sr32 for APB1 clock setup.
68fe29c sunxi: remove magic numbers from clock_get_pll{5,6}
c89867d sunxi: clocks: clock_get_pll5 prototype and coding style
501ab1e ARM: sunxi: Fix sun6i PLL6 settings
37f669b ARM: sunxi: Fix macro names for mmc and uart reset offsets
61de1e6 ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: styling fixes reported by checkpatch.pl]
[wens@csie.org: drop unsupported SPL code block and unused gpio.h header]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
205 lines
7.5 KiB
C
205 lines
7.5 KiB
C
/*
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* sun6i clock register definitions
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*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_CLOCK_SUN6I_H
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#define _SUNXI_CLOCK_SUN6I_H
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struct sunxi_ccm_reg {
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u32 pll1_cfg; /* 0x00 pll1 control */
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u32 reserved0;
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u32 pll2_cfg; /* 0x08 pll2 control */
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u32 reserved1;
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u32 pll3_cfg; /* 0x10 pll3 control */
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u32 reserved2;
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u32 pll4_cfg; /* 0x18 pll4 control */
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u32 reserved3;
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u32 pll5_cfg; /* 0x20 pll5 control */
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u32 reserved4;
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u32 pll6_cfg; /* 0x28 pll6 control */
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u32 reserved5;
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u32 pll7_cfg; /* 0x30 pll7 control */
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u32 reserved6;
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u32 pll8_cfg; /* 0x38 pll8 control */
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u32 reserved7;
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u32 mipi_pll_cfg; /* 0x40 MIPI pll control */
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u32 pll9_cfg; /* 0x44 pll9 control */
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u32 pll10_cfg; /* 0x48 pll10 control */
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u32 reserved8;
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u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */
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u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */
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u32 apb2_div; /* 0x58 APB2 divide ratio */
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u32 axi_gate; /* 0x5c axi module clock gating */
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u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
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u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
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u32 apb1_gate; /* 0x68 apb1 module clock gating */
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u32 apb2_gate; /* 0x6c apb2 module clock gating */
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u32 reserved9[4];
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u32 nand0_clk_cfg; /* 0x80 nand0 clock control */
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u32 nand1_clk_cfg; /* 0x84 nand1 clock control */
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u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
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u32 sd1_clk_cfg; /* 0x8c sd1 clock control */
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u32 sd2_clk_cfg; /* 0x90 sd2 clock control */
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u32 sd3_clk_cfg; /* 0x94 sd3 clock control */
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u32 ts_clk_cfg; /* 0x98 transport stream clock control */
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u32 ss_clk_cfg; /* 0x9c security system clock control */
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u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */
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u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */
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u32 spi2_clk_cfg; /* 0xa8 spi2 clock control */
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u32 spi3_clk_cfg; /* 0xac spi3 clock control */
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u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control*/
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u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */
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u32 reserved10[2];
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u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */
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u32 reserved11[2];
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u32 usb_clk_cfg; /* 0xcc USB clock control */
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u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */
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u32 reserved12[7];
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u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */
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u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */
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u32 reserved13[2];
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u32 dram_clk_gate; /* 0x100 DRAM module gating */
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u32 be0_clk_cfg; /* 0x104 BE0 module clock */
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u32 be1_clk_cfg; /* 0x108 BE1 module clock */
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u32 fe0_clk_cfg; /* 0x10c FE0 module clock */
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u32 fe1_clk_cfg; /* 0x110 FE1 module clock */
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u32 mp_clk_cfg; /* 0x114 MP module clock */
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u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */
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u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */
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u32 reserved14[3];
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u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */
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u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */
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u32 csi0_clk_cfg; /* 0x134 CSI0 module clock */
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u32 csi1_clk_cfg; /* 0x138 CSI1 module clock */
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u32 ve_clk_cfg; /* 0x13c VE module clock */
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u32 adda_clk_cfg; /* 0x140 ADDA module clock */
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u32 avs_clk_cfg; /* 0x144 AVS module clock */
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u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/
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u32 reserved15;
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u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */
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u32 ps_clk_cfg; /* 0x154 PS module clock */
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u32 mtc_clk_cfg; /* 0x158 MTC module clock */
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u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */
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u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */
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u32 reserved16;
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u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */
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u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */
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u32 reserved17[4];
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u32 iep_drc0_clk_cfg; /* 0x180 IEP DRC0 module clock */
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u32 iep_drc1_clk_cfg; /* 0x184 IEP DRC1 module clock */
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u32 iep_deu0_clk_cfg; /* 0x188 IEP DEU0 module clock */
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u32 iep_deu1_clk_cfg; /* 0x18c IEP DEU1 module clock */
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u32 reserved18[4];
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u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */
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u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */
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u32 gpu_hyd_clk_cfg; /* 0x1a0 GPU HYD clock config */
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u32 reserved19[21];
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u32 pll_lock; /* 0x200 PLL Lock Time */
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u32 pll1_lock; /* 0x204 PLL1 Lock Time */
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u32 reserved20[6];
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u32 pll1_bias_cfg; /* 0x220 PLL1 Bias config */
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u32 pll2_bias_cfg; /* 0x224 PLL2 Bias config */
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u32 pll3_bias_cfg; /* 0x228 PLL3 Bias config */
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u32 pll4_bias_cfg; /* 0x22c PLL4 Bias config */
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u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */
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u32 pll6_bias_cfg; /* 0x234 PLL6 Bias config */
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u32 pll7_bias_cfg; /* 0x238 PLL7 Bias config */
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u32 pll8_bias_cfg; /* 0x23c PLL8 Bias config */
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u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */
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u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */
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u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */
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u32 reserved21[13];
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u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */
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u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */
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u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */
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u32 pll4_pattern_cfg; /* 0x28c PLL4 Pattern config */
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u32 pll5_pattern_cfg; /* 0x290 PLL5 Pattern config */
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u32 pll6_pattern_cfg; /* 0x294 PLL6 Pattern config */
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u32 pll7_pattern_cfg; /* 0x298 PLL7 Pattern config */
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u32 pll8_pattern_cfg; /* 0x29c PLL8 Pattern config */
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u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */
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u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */
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u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */
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u32 reserved22[5];
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u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */
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u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */
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u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */
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u32 reserved23;
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u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */
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u32 reserved24;
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u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */
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};
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/* apb2 bit field */
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#define APB2_CLK_SRC_LOSC (0x0 << 24)
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#define APB2_CLK_SRC_OSC24M (0x1 << 24)
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#define APB2_CLK_SRC_PLL6 (0x2 << 24)
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#define APB2_CLK_SRC_MASK (0x3 << 24)
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#define APB2_CLK_RATE_N_1 (0x0 << 16)
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#define APB2_CLK_RATE_N_2 (0x1 << 16)
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#define APB2_CLK_RATE_N_4 (0x2 << 16)
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#define APB2_CLK_RATE_N_8 (0x3 << 16)
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#define APB2_CLK_RATE_N_MASK (3 << 16)
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#define APB2_CLK_RATE_M(m) (((m)-1) << 0)
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#define APB2_CLK_RATE_M_MASK (0x1f << 0)
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/* apb2 gate field */
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#define APB2_GATE_UART_SHIFT (16)
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#define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT)
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#define APB2_GATE_TWI_SHIFT (0)
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#define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT)
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/* cpu_axi_cfg bits */
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#define AXI_DIV_SHIFT 0
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#define ATB_DIV_SHIFT 8
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#define CPU_CLK_SRC_SHIFT 16
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#define AXI_DIV_1 0
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#define AXI_DIV_2 1
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#define AXI_DIV_3 2
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#define AXI_DIV_4 3
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#define ATB_DIV_1 0
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#define ATB_DIV_2 1
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#define ATB_DIV_4 2
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#define CPU_CLK_SRC_OSC24M 1
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#define CPU_CLK_SRC_PLL1 2
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#define PLL1_CFG_DEFAULT 0x90011b21
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#define PLL6_CFG_DEFAULT 0x90041811
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#define CCM_PLL6_CTRL_N_SHIFT 8
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#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
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#define CCM_PLL6_CTRL_K_SHIFT 4
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#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
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#define AHB_GATE_OFFSET_MMC3 11
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#define AHB_GATE_OFFSET_MMC2 10
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#define AHB_GATE_OFFSET_MMC1 9
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#define AHB_GATE_OFFSET_MMC0 8
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#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
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#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
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#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
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#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
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#define AHB_RESET_OFFSET_MMC3 11
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#define AHB_RESET_OFFSET_MMC2 10
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#define AHB_RESET_OFFSET_MMC1 9
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#define AHB_RESET_OFFSET_MMC0 8
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#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n))
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/* apb2 reset */
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#define APB2_RESET_UART_SHIFT (16)
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#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
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#define APB2_RESET_TWI_SHIFT (0)
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#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT)
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#endif /* _SUNXI_CLOCK_SUN6I_H */
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