mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-30 03:12:07 +00:00
2564fce7ee
According to their TRMs, Cortex ARMv7 CPUs with SMP support require the ACTLR.SMPEN bit to be set as early as possible, before any cache or TLB maintenance operations are done. As we do those things still in start.S, we need to move the SMPEN bit setting there, too. This introduces a new ARMv7 wide symbol and code to set bit 6 in ACTLR very early in start.S, and moves sunxi boards over to use that instead of the custom code we had in our board.c file (where it was called technically too late). In practice we got away with this so far, because at this point all the other cores were still in reset, so any broadcasting would have been ignored anyway. But it is architecturally cleaner to do it early, and we move a core specific piece of code out of board.c. This also gets rid of the ARM_CORTEX_CPU_IS_UP kludge I introduced a few years back, and moves the respective logic into the new Kconfig entry. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
396 lines
12 KiB
ArmAsm
396 lines
12 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
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*
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* Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
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*
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* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
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* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
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* Copyright (c) 2003 Kshitij <kshitij@ti.com>
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* Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/system.h>
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#include <linux/linkage.h>
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#include <asm/armv7.h>
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/*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* Do important init only if we don't start from memory!
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* Setup memory and board specific bits prior to relocation.
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* Relocate armboot to ram. Setup stack.
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*
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*************************************************************************/
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.globl reset
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.globl save_boot_params_ret
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.type save_boot_params_ret,%function
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#ifdef CONFIG_ARMV7_LPAE
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.global switch_to_hypervisor_ret
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#endif
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reset:
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/* Allow the board to save important registers */
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b save_boot_params
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save_boot_params_ret:
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#ifdef CONFIG_POSITION_INDEPENDENT
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/*
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* Fix .rela.dyn relocations. This allows U-Boot to loaded to and
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* executed at a different address than it was linked at.
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*/
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pie_fixup:
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adr r0, reset /* r0 <- Runtime value of reset label */
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ldr r1, =reset /* r1 <- Linked value of reset label */
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subs r4, r0, r1 /* r4 <- Runtime-vs-link offset */
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beq pie_fixup_done
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adr r0, pie_fixup
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ldr r1, _rel_dyn_start_ofs
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add r2, r0, r1 /* r2 <- Runtime &__rel_dyn_start */
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ldr r1, _rel_dyn_end_ofs
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add r3, r0, r1 /* r3 <- Runtime &__rel_dyn_end */
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pie_fix_loop:
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ldr r0, [r2] /* r0 <- Link location */
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ldr r1, [r2, #4] /* r1 <- fixup */
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cmp r1, #23 /* relative fixup? */
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bne pie_skip_reloc
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/* relative fix: increase location by offset */
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add r0, r4
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ldr r1, [r0]
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add r1, r4
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str r1, [r0]
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str r0, [r2]
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add r2, #8
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pie_skip_reloc:
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cmp r2, r3
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blo pie_fix_loop
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pie_fixup_done:
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#endif
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#ifdef CONFIG_ARMV7_LPAE
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/*
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* check for Hypervisor support
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*/
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mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
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and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
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cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
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beq switch_to_hypervisor
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switch_to_hypervisor_ret:
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#endif
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/*
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* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
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* except if in HYP mode already
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*/
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mrs r0, cpsr
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and r1, r0, #0x1f @ mask mode bits
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teq r1, #0x1a @ test for HYP mode
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bicne r0, r0, #0x1f @ clear all mode bits
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orrne r0, r0, #0x13 @ set SVC mode
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orr r0, r0, #0xc0 @ disable FIQ and IRQ
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msr cpsr,r0
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/*
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* Setup vector:
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* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
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* Continue to use ROM code vector only in OMAP4 spl)
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*/
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#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
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/* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
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mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
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bic r0, #CR_V @ V = 0
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mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
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#ifdef CONFIG_HAS_VBAR
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/* Set vector address in CP15 VBAR register */
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ldr r0, =_start
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mcr p15, 0, r0, c12, c0, 0 @Set VBAR
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#endif
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#endif
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/* the mask ROM code should have PLL and others stable */
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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#ifdef CONFIG_CPU_V7A
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bl cpu_init_cp15
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#endif
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
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bl cpu_init_crit
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#endif
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#endif
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bl _main
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/*------------------------------------------------------------------------------*/
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ENTRY(c_runtime_cpu_setup)
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/*
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* If I-cache is enabled invalidate it
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*/
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#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
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mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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#endif
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bx lr
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ENDPROC(c_runtime_cpu_setup)
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/*************************************************************************
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*
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* void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
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* __attribute__((weak));
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*
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* Stack pointer is not yet initialized at this moment
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* Don't save anything to stack even if compiled with -O0
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*
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*************************************************************************/
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ENTRY(save_boot_params)
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b save_boot_params_ret @ back to my caller
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ENDPROC(save_boot_params)
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.weak save_boot_params
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#ifdef CONFIG_ARMV7_LPAE
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ENTRY(switch_to_hypervisor)
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b switch_to_hypervisor_ret
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ENDPROC(switch_to_hypervisor)
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.weak switch_to_hypervisor
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#endif
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/*************************************************************************
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*
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* cpu_init_cp15
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*
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* Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
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* CONFIG_SYS_ICACHE_OFF is defined.
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*
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*************************************************************************/
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ENTRY(cpu_init_cp15)
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#if CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN)
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/*
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* The Arm Cortex-A7 TRM says this bit must be enabled before
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* "any cache or TLB maintenance operations are performed".
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*/
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mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
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orr r0, r0, #1 << 6 @ set SMP bit to enable coherency
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mcr p15, 0, r0, c1, c0, 1 @ write auxilary control register
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#endif
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/*
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* Invalidate L1 I/D
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*/
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mov r0, #0 @ set up for MCR
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mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
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bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
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orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
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orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
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#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
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bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
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#else
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
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#endif
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mcr p15, 0, r0, c1, c0, 0
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#ifdef CONFIG_ARM_ERRATA_716044
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mrc p15, 0, r0, c1, c0, 0 @ read system control register
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orr r0, r0, #1 << 11 @ set bit #11
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mcr p15, 0, r0, c1, c0, 0 @ write system control register
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#endif
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#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 4 @ set bit #4
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_743622
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 6 @ set bit #6
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_751472
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 11 @ set bit #11
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_761320
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 21 @ set bit #21
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_845369
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 22 @ set bit #22
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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mov r5, lr @ Store my Caller
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mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
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mov r3, r1, lsr #20 @ get variant field
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and r3, r3, #0xf @ r3 has CPU variant
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and r4, r1, #0xf @ r4 has CPU revision
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mov r2, r3, lsl #4 @ shift variant field for combined value
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orr r2, r4, r2 @ r2 has combined CPU variant + revision
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/* Early stack for ERRATA that needs into call C code */
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
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ldr r0, =(CONFIG_SPL_STACK)
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#else
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ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)
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#endif
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bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
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mov sp, r0
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#ifdef CONFIG_ARM_ERRATA_798870
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cmp r2, #0x30 @ Applies to lower than R3p0
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bge skip_errata_798870 @ skip if not affected rev
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cmp r2, #0x20 @ Applies to including and above R2p0
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blt skip_errata_798870 @ skip if not affected rev
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mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg
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orr r0, r0, #1 << 7 @ Enable hazard-detect timeout
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push {r1-r5} @ Save the cpu info registers
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bl v7_arch_cp15_set_l2aux_ctrl
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isb @ Recommended ISB after l2actlr update
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pop {r1-r5} @ Restore the cpu info - fall through
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skip_errata_798870:
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#endif
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#ifdef CONFIG_ARM_ERRATA_801819
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cmp r2, #0x24 @ Applies to lt including R2p4
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bgt skip_errata_801819 @ skip if not affected rev
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cmp r2, #0x20 @ Applies to including and above R2p0
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blt skip_errata_801819 @ skip if not affected rev
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mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg
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and r0, r0, #1 << 3 @ check REVIDR[3]
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cmp r0, #1 << 3
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beq skip_errata_801819 @ skip erratum if REVIDR[3] is set
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mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
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orr r0, r0, #3 << 27 @ Disables streaming. All write-allocate
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@ lines allocate in the L1 or L2 cache.
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orr r0, r0, #3 << 25 @ Disables streaming. All write-allocate
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@ lines allocate in the L1 cache.
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push {r1-r5} @ Save the cpu info registers
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bl v7_arch_cp15_set_acr
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pop {r1-r5} @ Restore the cpu info - fall through
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skip_errata_801819:
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#endif
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#ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715
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mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
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orr r0, r0, #1 << 0 @ Enable invalidates of BTB
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push {r1-r5} @ Save the cpu info registers
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bl v7_arch_cp15_set_acr
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pop {r1-r5} @ Restore the cpu info - fall through
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#endif
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#ifdef CONFIG_ARM_ERRATA_454179
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mrc p15, 0, r0, c1, c0, 1 @ Read ACR
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cmp r2, #0x21 @ Only on < r2p1
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orrlt r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
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push {r1-r5} @ Save the cpu info registers
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bl v7_arch_cp15_set_acr
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pop {r1-r5} @ Restore the cpu info - fall through
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#endif
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#if defined(CONFIG_ARM_ERRATA_430973) || defined (CONFIG_ARM_CORTEX_A8_CVE_2017_5715)
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mrc p15, 0, r0, c1, c0, 1 @ Read ACR
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#ifdef CONFIG_ARM_CORTEX_A8_CVE_2017_5715
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orr r0, r0, #(0x1 << 6) @ Set IBE bit always to enable OS WA
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#else
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cmp r2, #0x21 @ Only on < r2p1
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orrlt r0, r0, #(0x1 << 6) @ Set IBE bit
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#endif
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push {r1-r5} @ Save the cpu info registers
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bl v7_arch_cp15_set_acr
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pop {r1-r5} @ Restore the cpu info - fall through
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#endif
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#ifdef CONFIG_ARM_ERRATA_621766
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mrc p15, 0, r0, c1, c0, 1 @ Read ACR
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cmp r2, #0x21 @ Only on < r2p1
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orrlt r0, r0, #(0x1 << 5) @ Set L1NEON bit
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push {r1-r5} @ Save the cpu info registers
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bl v7_arch_cp15_set_acr
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pop {r1-r5} @ Restore the cpu info - fall through
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#endif
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#ifdef CONFIG_ARM_ERRATA_725233
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mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR
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cmp r2, #0x21 @ Only on < r2p1 (Cortex A8)
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orrlt r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable
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push {r1-r5} @ Save the cpu info registers
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bl v7_arch_cp15_set_l2aux_ctrl
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pop {r1-r5} @ Restore the cpu info - fall through
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#endif
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#ifdef CONFIG_ARM_ERRATA_852421
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 24 @ set bit #24
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_852423
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 12 @ set bit #12
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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mov pc, r5 @ back to my caller
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ENDPROC(cpu_init_cp15)
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
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!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
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/*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************/
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ENTRY(cpu_init_crit)
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/*
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* Jump to board specific initialization...
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* The Mask ROM will have already initialized
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* basic memory. Go here to bump up clock rate and handle
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* wake up conditions.
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*/
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b lowlevel_init @ go setup pll,mux,memory
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ENDPROC(cpu_init_crit)
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#endif
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#if CONFIG_POSITION_INDEPENDENT
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_rel_dyn_start_ofs:
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.word __rel_dyn_start - pie_fixup
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_rel_dyn_end_ofs:
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.word __rel_dyn_end - pie_fixup
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#endif
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