Kever Yang 3a94d75d0e rockchip: clk: update dwmmc clock div ... dwmmc controller has default internal divider by 2, and we always provide double of the clock rate request by dwmmc controller. Sync code for all Rockchip SoC with: 4055b46 rockchip: clk: rk3288: fix mmc clock setting Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [fixup for 'missing DIV_ROUND_UP' conflict for clk_rk3288.c:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>		2017-08-13 17:15:09 +02:00
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clk_rk322x.c	rockchip: clk: update dwmmc clock div	2017-08-13 17:15:09 +02:00
clk_rk3036.c	rockchip: clk: update dwmmc clock div	2017-08-13 17:15:09 +02:00
clk_rk3188.c	rockchip: clk: update dwmmc clock div	2017-08-13 17:15:09 +02:00
clk_rk3288.c	rockchip: clk: update dwmmc clock div	2017-08-13 17:15:09 +02:00
clk_rk3328.c	rockchip: clk: update dwmmc clock div	2017-08-13 17:15:09 +02:00
clk_rk3368.c	rockchip: clk: rk3368: add support for configuring the SPI clocks	2017-08-13 17:12:33 +02:00
clk_rk3399.c	rockchip: clk: update dwmmc clock div	2017-08-13 17:15:09 +02:00
clk_rv1108.c	clk_rv1108.c: Fix unused variable warning	2017-06-23 10:38:05 -04:00
Makefile	rockchip: rk322x: add clock driver	2017-07-11 12:13:45 +02:00