mirror of
https://github.com/AsahiLinux/u-boot
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3a88179d03
Linker script is not able find start.o binary. So add its absolute path in u-boot-spl.lds. This change is similar to u-boot-nand.lds common/Makefile: Avoid compiling unnecssary files fsl_ifc_spl.c : It is is responsible for reading u-boot binary from NAND flash and copying into DDR. It also transfer control from NAND SPL to u-boot image present in DDR. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
258 lines
6.5 KiB
C
258 lines
6.5 KiB
C
/*
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* NAND boot for Freescale Integrated Flash Controller, NAND FCM
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*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Author: Dipen Dudhat <dipen.dudhat@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/fsl_ifc.h>
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#include <linux/mtd/nand.h>
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static inline int is_blank(uchar *addr, int page_size)
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{
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int i;
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for (i = 0; i < page_size; i++) {
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if (__raw_readb(&addr[i]) != 0xff)
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return 0;
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}
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/*
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* For the SPL, don't worry about uncorrectable errors
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* where the main area is all FFs but shouldn't be.
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*/
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return 1;
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}
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/* returns nonzero if entire page is blank */
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static inline int check_read_ecc(uchar *buf, u32 *eccstat,
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unsigned int bufnum, int page_size)
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{
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u32 reg = eccstat[bufnum / 4];
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int errors = (reg >> ((3 - bufnum % 4) * 8)) & 0xf;
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if (errors == 0xf) { /* uncorrectable */
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/* Blank pages fail hw ECC checks */
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if (is_blank(buf, page_size))
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return 1;
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puts("ecc error\n");
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for (;;)
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;
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}
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return 0;
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}
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static inline void nand_wait(uchar *buf, int bufnum, int page_size)
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{
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struct fsl_ifc *ifc = IFC_BASE_ADDR;
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u32 status;
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u32 eccstat[4];
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int bufperpage = page_size / 512;
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int bufnum_end, i;
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bufnum *= bufperpage;
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bufnum_end = bufnum + bufperpage - 1;
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do {
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status = in_be32(&ifc->ifc_nand.nand_evter_stat);
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} while (!(status & IFC_NAND_EVTER_STAT_OPC));
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if (status & IFC_NAND_EVTER_STAT_FTOER) {
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puts("flash time out error\n");
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for (;;)
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;
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}
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for (i = bufnum / 4; i <= bufnum_end / 4; i++)
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eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
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for (i = bufnum; i <= bufnum_end; i++) {
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if (check_read_ecc(buf, eccstat, i, page_size))
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break;
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}
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out_be32(&ifc->ifc_nand.nand_evter_stat, status);
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}
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static inline int bad_block(uchar *marker, int port_size)
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{
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if (port_size == 8)
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return __raw_readb(marker) != 0xff;
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else
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return __raw_readw((u16 *)marker) != 0xffff;
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}
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static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
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{
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struct fsl_ifc *ifc = IFC_BASE_ADDR;
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uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
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int page_size;
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int port_size;
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int pages_per_blk;
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int blk_size;
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int bad_marker = 0;
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int bufnum_mask, bufnum;
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int csor, cspr;
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int pos = 0;
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int j = 0;
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int sram_addr;
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int pg_no;
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/* Get NAND Flash configuration */
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csor = CONFIG_SYS_NAND_CSOR;
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cspr = CONFIG_SYS_NAND_CSPR;
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port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
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if (csor & CSOR_NAND_PGS_4K) {
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page_size = 4096;
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bufnum_mask = 0x1;
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} else if (csor & CSOR_NAND_PGS_2K) {
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page_size = 2048;
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bufnum_mask = 0x3;
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} else {
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page_size = 512;
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bufnum_mask = 0xf;
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if (port_size == 8)
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bad_marker = 5;
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}
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pages_per_blk =
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32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
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blk_size = pages_per_blk * page_size;
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/* Open Full SRAM mapping for spare are access */
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out_be32(&ifc->ifc_nand.ncfgr, 0x0);
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/* Clear Boot events */
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out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
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/* Program FIR/FCR for Large/Small page */
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if (page_size > 512) {
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out_be32(&ifc->ifc_nand.nand_fir0,
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
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(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
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(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
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(IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
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out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
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out_be32(&ifc->ifc_nand.nand_fcr0,
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(NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
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(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
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} else {
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out_be32(&ifc->ifc_nand.nand_fir0,
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
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(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
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(IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
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out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
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out_be32(&ifc->ifc_nand.nand_fcr0,
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NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
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}
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/* Program FBCR = 0 for full page read */
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out_be32(&ifc->ifc_nand.nand_fbcr, 0);
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/* Read and copy u-boot on SDRAM from NAND device, In parallel
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* check for Bad block if found skip it and read continue to
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* next Block
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*/
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while (pos < uboot_size) {
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int i = 0;
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do {
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pg_no = offs / page_size;
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bufnum = pg_no & bufnum_mask;
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sram_addr = bufnum * page_size * 2;
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out_be32(&ifc->ifc_nand.row0, pg_no);
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out_be32(&ifc->ifc_nand.col0, 0);
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/* start read */
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out_be32(&ifc->ifc_nand.nandseq_strt,
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IFC_NAND_SEQ_STRT_FIR_STRT);
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/* wait for read to complete */
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nand_wait(&buf[sram_addr], bufnum, page_size);
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/*
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* If either of the first two pages are marked bad,
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* continue to the next block.
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*/
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if (i++ < 2 &&
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bad_block(&buf[sram_addr + page_size + bad_marker],
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port_size)) {
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puts("skipping\n");
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offs = (offs + blk_size) & ~(blk_size - 1);
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pos &= ~(blk_size - 1);
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break;
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}
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for (j = 0; j < page_size; j++)
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dst[pos + j] = __raw_readb(&buf[sram_addr + j]);
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pos += page_size;
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offs += page_size;
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} while ((offs & (blk_size - 1)) && (pos < uboot_size));
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}
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}
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/*
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* Main entrypoint for NAND Boot. It's necessary that SDRAM is already
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* configured and available since this code loads the main U-boot image
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* from NAND into SDRAM and starts from there.
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*/
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void nand_boot(void)
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{
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__attribute__((noreturn)) void (*uboot)(void);
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/*
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* Load U-Boot image from NAND into RAM
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*/
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nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
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(uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
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#ifdef CONFIG_NAND_ENV_DST
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nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(uchar *)CONFIG_NAND_ENV_DST);
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#ifdef CONFIG_ENV_OFFSET_REDUND
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nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
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(uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
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#endif
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#endif
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/*
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* Jump to U-Boot image
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*/
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#ifdef CONFIG_SPL_FLUSH_IMAGE
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/*
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* Clean d-cache and invalidate i-cache, to
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* make sure that no stale data is executed.
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*/
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flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
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#endif
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uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
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uboot();
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}
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