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find . -name '*.c' -exec \
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Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
661 lines
18 KiB
C
661 lines
18 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Defines APIs and structures that allow software to interact with a
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* TPM2 device
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*
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* Copyright (c) 2020 Linaro
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* Copyright (c) 2018 Bootlin
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*
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* https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/
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*
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* Author: Miquel Raynal <miquel.raynal@bootlin.com>
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*/
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#ifndef __TPM_V2_H
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#define __TPM_V2_H
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#include <tpm-common.h>
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struct udevice;
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#define TPM2_DIGEST_LEN 32
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#define TPM2_SHA1_DIGEST_SIZE 20
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#define TPM2_SHA256_DIGEST_SIZE 32
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#define TPM2_SHA384_DIGEST_SIZE 48
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#define TPM2_SHA512_DIGEST_SIZE 64
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#define TPM2_SM3_256_DIGEST_SIZE 32
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#define TPM2_MAX_PCRS 32
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#define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8)
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#define TPM2_MAX_CAP_BUFFER 1024
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#define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \
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sizeof(u32)) / sizeof(struct tpms_tagged_property))
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#define TPM2_HDR_LEN 10
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/*
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* We deviate from this draft of the specification by increasing the value of
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* TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2
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* implementations that have enabled a larger than typical number of PCR
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* banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included
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* in a future revision of the specification.
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*/
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#define TPM2_NUM_PCR_BANKS 16
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/* Definition of (UINT32) TPM2_CAP Constants */
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#define TPM2_CAP_PCRS 0x00000005U
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#define TPM2_CAP_TPM_PROPERTIES 0x00000006U
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/* Definition of (UINT32) TPM2_PT Constants */
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#define TPM2_PT_GROUP (u32)(0x00000100)
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#define TPM2_PT_FIXED (u32)(TPM2_PT_GROUP * 1)
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#define TPM2_PT_MANUFACTURER (u32)(TPM2_PT_FIXED + 5)
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#define TPM2_PT_PCR_COUNT (u32)(TPM2_PT_FIXED + 18)
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#define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30)
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#define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31)
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/*
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* event types, cf.
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* "TCG Server Management Domain Firmware Profile Specification",
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* rev 1.00, 2020-05-01
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*/
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#define EV_POST_CODE ((u32)0x00000001)
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#define EV_NO_ACTION ((u32)0x00000003)
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#define EV_SEPARATOR ((u32)0x00000004)
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#define EV_ACTION ((u32)0x00000005)
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#define EV_TAG ((u32)0x00000006)
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#define EV_S_CRTM_CONTENTS ((u32)0x00000007)
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#define EV_S_CRTM_VERSION ((u32)0x00000008)
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#define EV_CPU_MICROCODE ((u32)0x00000009)
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#define EV_PLATFORM_CONFIG_FLAGS ((u32)0x0000000A)
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#define EV_TABLE_OF_DEVICES ((u32)0x0000000B)
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#define EV_COMPACT_HASH ((u32)0x0000000C)
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/*
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* event types, cf.
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* "TCG PC Client Platform Firmware Profile Specification", Family "2.0"
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* Level 00 Version 1.05 Revision 23, May 7, 2021
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*/
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#define EV_EFI_EVENT_BASE ((u32)0x80000000)
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#define EV_EFI_VARIABLE_DRIVER_CONFIG ((u32)0x80000001)
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#define EV_EFI_VARIABLE_BOOT ((u32)0x80000002)
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#define EV_EFI_BOOT_SERVICES_APPLICATION ((u32)0x80000003)
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#define EV_EFI_BOOT_SERVICES_DRIVER ((u32)0x80000004)
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#define EV_EFI_RUNTIME_SERVICES_DRIVER ((u32)0x80000005)
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#define EV_EFI_GPT_EVENT ((u32)0x80000006)
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#define EV_EFI_ACTION ((u32)0x80000007)
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#define EV_EFI_PLATFORM_FIRMWARE_BLOB ((u32)0x80000008)
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#define EV_EFI_HANDOFF_TABLES ((u32)0x80000009)
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#define EV_EFI_PLATFORM_FIRMWARE_BLOB2 ((u32)0x8000000A)
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#define EV_EFI_HANDOFF_TABLES2 ((u32)0x8000000B)
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#define EV_EFI_VARIABLE_BOOT2 ((u32)0x8000000C)
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#define EV_EFI_HCRTM_EVENT ((u32)0x80000010)
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#define EV_EFI_VARIABLE_AUTHORITY ((u32)0x800000E0)
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#define EV_EFI_SPDM_FIRMWARE_BLOB ((u32)0x800000E1)
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#define EV_EFI_SPDM_FIRMWARE_CONFIG ((u32)0x800000E2)
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#define EFI_CALLING_EFI_APPLICATION \
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"Calling EFI Application from Boot Option"
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#define EFI_RETURNING_FROM_EFI_APPLICATION \
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"Returning from EFI Application from Boot Option"
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#define EFI_EXIT_BOOT_SERVICES_INVOCATION \
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"Exit Boot Services Invocation"
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#define EFI_EXIT_BOOT_SERVICES_FAILED \
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"Exit Boot Services Returned with Failure"
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#define EFI_EXIT_BOOT_SERVICES_SUCCEEDED \
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"Exit Boot Services Returned with Success"
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/* TPMS_TAGGED_PROPERTY Structure */
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struct tpms_tagged_property {
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u32 property;
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u32 value;
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} __packed;
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/* TPMS_PCR_SELECTION Structure */
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struct tpms_pcr_selection {
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u16 hash;
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u8 size_of_select;
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u8 pcr_select[TPM2_PCR_SELECT_MAX];
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} __packed;
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/* TPML_PCR_SELECTION Structure */
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struct tpml_pcr_selection {
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u32 count;
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struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS];
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} __packed;
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/* TPML_TAGGED_TPM_PROPERTY Structure */
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struct tpml_tagged_tpm_property {
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u32 count;
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struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES];
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} __packed;
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/* TPMU_CAPABILITIES Union */
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union tpmu_capabilities {
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/*
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* Non exhaustive. Only added the structs needed for our
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* current code
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*/
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struct tpml_pcr_selection assigned_pcr;
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struct tpml_tagged_tpm_property tpm_properties;
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} __packed;
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/* TPMS_CAPABILITY_DATA Structure */
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struct tpms_capability_data {
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u32 capability;
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union tpmu_capabilities data;
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} __packed;
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/**
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* SHA1 Event Log Entry Format
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*
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* @pcr_index: PCRIndex event extended to
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* @event_type: Type of event (see EFI specs)
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* @digest: Value extended into PCR index
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* @event_size: Size of event
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* @event: Event data
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*/
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struct tcg_pcr_event {
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u32 pcr_index;
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u32 event_type;
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u8 digest[TPM2_SHA1_DIGEST_SIZE];
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u32 event_size;
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u8 event[];
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} __packed;
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/**
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* Definition of TPMU_HA Union
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*/
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union tmpu_ha {
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u8 sha1[TPM2_SHA1_DIGEST_SIZE];
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u8 sha256[TPM2_SHA256_DIGEST_SIZE];
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u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE];
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u8 sha384[TPM2_SHA384_DIGEST_SIZE];
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u8 sha512[TPM2_SHA512_DIGEST_SIZE];
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} __packed;
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/**
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* Definition of TPMT_HA Structure
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*
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* @hash_alg: Hash algorithm defined in enum tpm2_algorithms
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* @digest: Digest value for a given algorithm
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*/
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struct tpmt_ha {
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u16 hash_alg;
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union tmpu_ha digest;
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} __packed;
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/**
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* Definition of TPML_DIGEST_VALUES Structure
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*
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* @count: Number of algorithms supported by hardware
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* @digests: struct for algorithm id and hash value
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*/
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struct tpml_digest_values {
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u32 count;
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struct tpmt_ha digests[TPM2_NUM_PCR_BANKS];
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} __packed;
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/**
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* Crypto Agile Log Entry Format
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*
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* @pcr_index: PCRIndex event extended to
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* @event_type: Type of event
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* @digests: List of digestsextended to PCR index
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* @event_size: Size of the event data
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* @event: Event data
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*/
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struct tcg_pcr_event2 {
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u32 pcr_index;
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u32 event_type;
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struct tpml_digest_values digests;
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u32 event_size;
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u8 event[];
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} __packed;
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/**
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* TPM2 Structure Tags for command/response buffers.
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*
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* @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
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* @TPM2_ST_SESSIONS: the command needs an authentication.
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*/
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enum tpm2_structures {
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TPM2_ST_NO_SESSIONS = 0x8001,
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TPM2_ST_SESSIONS = 0x8002,
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};
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/**
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* TPM2 type of boolean.
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*/
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enum tpm2_yes_no {
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TPMI_YES = 1,
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TPMI_NO = 0,
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};
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/**
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* TPM2 startup values.
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*
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* @TPM2_SU_CLEAR: reset the internal state.
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* @TPM2_SU_STATE: restore saved state (if any).
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*/
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enum tpm2_startup_types {
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TPM2_SU_CLEAR = 0x0000,
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TPM2_SU_STATE = 0x0001,
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};
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/**
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* TPM2 permanent handles.
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*
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* @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
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* @TPM2_RS_PW: indicates a password.
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* @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
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* @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
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* @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
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*/
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enum tpm2_handles {
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TPM2_RH_OWNER = 0x40000001,
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TPM2_RS_PW = 0x40000009,
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TPM2_RH_LOCKOUT = 0x4000000A,
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TPM2_RH_ENDORSEMENT = 0x4000000B,
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TPM2_RH_PLATFORM = 0x4000000C,
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};
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/**
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* TPM2 command codes used at the beginning of a buffer, gives the command.
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*
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* @TPM2_CC_STARTUP: TPM2_Startup().
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* @TPM2_CC_SELF_TEST: TPM2_SelfTest().
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* @TPM2_CC_CLEAR: TPM2_Clear().
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* @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
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* @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
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* @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
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* @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
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* @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
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* @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
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* @TPM2_CC_GET_RANDOM: TPM2_GetRandom().
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* @TPM2_CC_PCR_READ: TPM2_PCR_Read().
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* @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
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* @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
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*/
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enum tpm2_command_codes {
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TPM2_CC_STARTUP = 0x0144,
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TPM2_CC_SELF_TEST = 0x0143,
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TPM2_CC_HIER_CONTROL = 0x0121,
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TPM2_CC_CLEAR = 0x0126,
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TPM2_CC_CLEARCONTROL = 0x0127,
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TPM2_CC_HIERCHANGEAUTH = 0x0129,
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TPM2_CC_NV_DEFINE_SPACE = 0x012a,
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TPM2_CC_PCR_SETAUTHPOL = 0x012C,
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TPM2_CC_NV_WRITE = 0x0137,
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TPM2_CC_NV_WRITELOCK = 0x0138,
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TPM2_CC_DAM_RESET = 0x0139,
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TPM2_CC_DAM_PARAMETERS = 0x013A,
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TPM2_CC_NV_READ = 0x014E,
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TPM2_CC_GET_CAPABILITY = 0x017A,
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TPM2_CC_GET_RANDOM = 0x017B,
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TPM2_CC_PCR_READ = 0x017E,
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TPM2_CC_PCR_EXTEND = 0x0182,
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TPM2_CC_PCR_SETAUTHVAL = 0x0183,
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};
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/**
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* TPM2 return codes.
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*/
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enum tpm2_return_codes {
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TPM2_RC_SUCCESS = 0x0000,
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TPM2_RC_BAD_TAG = 0x001E,
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TPM2_RC_FMT1 = 0x0080,
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TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003,
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TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004,
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TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015,
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TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022,
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TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B,
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TPM2_RC_VER1 = 0x0100,
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TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000,
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TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001,
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TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020,
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TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025,
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TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043,
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TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044,
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TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045,
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TPM2_RC_NV_DEFINED = TPM2_RC_VER1 + 0x004c,
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TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053,
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TPM2_RC_WARN = 0x0900,
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TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A,
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TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010,
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TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021,
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};
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/**
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* TPM2 algorithms.
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*/
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enum tpm2_algorithms {
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TPM2_ALG_SHA1 = 0x04,
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TPM2_ALG_XOR = 0x0A,
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TPM2_ALG_SHA256 = 0x0B,
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TPM2_ALG_SHA384 = 0x0C,
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TPM2_ALG_SHA512 = 0x0D,
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TPM2_ALG_NULL = 0x10,
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TPM2_ALG_SM3_256 = 0x12,
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};
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/* NV index attributes */
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enum tpm_index_attrs {
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TPMA_NV_PPWRITE = 1UL << 0,
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TPMA_NV_OWNERWRITE = 1UL << 1,
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TPMA_NV_AUTHWRITE = 1UL << 2,
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TPMA_NV_POLICYWRITE = 1UL << 3,
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TPMA_NV_COUNTER = 1UL << 4,
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TPMA_NV_BITS = 1UL << 5,
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TPMA_NV_EXTEND = 1UL << 6,
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TPMA_NV_POLICY_DELETE = 1UL << 10,
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TPMA_NV_WRITELOCKED = 1UL << 11,
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TPMA_NV_WRITEALL = 1UL << 12,
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TPMA_NV_WRITEDEFINE = 1UL << 13,
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TPMA_NV_WRITE_STCLEAR = 1UL << 14,
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TPMA_NV_GLOBALLOCK = 1UL << 15,
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TPMA_NV_PPREAD = 1UL << 16,
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TPMA_NV_OWNERREAD = 1UL << 17,
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TPMA_NV_AUTHREAD = 1UL << 18,
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TPMA_NV_POLICYREAD = 1UL << 19,
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TPMA_NV_NO_DA = 1UL << 25,
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TPMA_NV_ORDERLY = 1UL << 26,
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TPMA_NV_CLEAR_STCLEAR = 1UL << 27,
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TPMA_NV_READLOCKED = 1UL << 28,
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TPMA_NV_WRITTEN = 1UL << 29,
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TPMA_NV_PLATFORMCREATE = 1UL << 30,
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TPMA_NV_READ_STCLEAR = 1UL << 31,
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TPMA_NV_MASK_READ = TPMA_NV_PPREAD | TPMA_NV_OWNERREAD |
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TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD,
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TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE |
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TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE,
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};
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enum {
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TPM_ACCESS_VALID = 1 << 7,
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TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5,
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TPM_ACCESS_REQUEST_PENDING = 1 << 2,
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TPM_ACCESS_REQUEST_USE = 1 << 1,
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TPM_ACCESS_ESTABLISHMENT = 1 << 0,
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};
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enum {
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TPM_STS_FAMILY_SHIFT = 26,
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TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT,
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TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT,
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TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25,
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TPM_STS_COMMAND_CANCEL = 1 << 24,
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TPM_STS_BURST_COUNT_SHIFT = 8,
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TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT,
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TPM_STS_VALID = 1 << 7,
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TPM_STS_COMMAND_READY = 1 << 6,
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TPM_STS_GO = 1 << 5,
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TPM_STS_DATA_AVAIL = 1 << 4,
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TPM_STS_DATA_EXPECT = 1 << 3,
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TPM_STS_SELF_TEST_DONE = 1 << 2,
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TPM_STS_RESPONSE_RETRY = 1 << 1,
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TPM_STS_READ_ZERO = 0x23
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};
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enum {
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TPM_CMD_COUNT_OFFSET = 2,
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TPM_CMD_ORDINAL_OFFSET = 6,
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TPM_MAX_BUF_SIZE = 1260,
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};
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enum {
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/* Secure storage for firmware settings */
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TPM_HT_PCR = 0,
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TPM_HT_NV_INDEX,
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TPM_HT_HMAC_SESSION,
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TPM_HT_POLICY_SESSION,
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HR_SHIFT = 24,
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HR_PCR = TPM_HT_PCR << HR_SHIFT,
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HR_HMAC_SESSION = TPM_HT_HMAC_SESSION << HR_SHIFT,
|
|
HR_POLICY_SESSION = TPM_HT_POLICY_SESSION << HR_SHIFT,
|
|
HR_NV_INDEX = TPM_HT_NV_INDEX << HR_SHIFT,
|
|
};
|
|
|
|
/**
|
|
* Issue a TPM2_Startup command.
|
|
*
|
|
* @dev TPM device
|
|
* @mode TPM startup mode
|
|
*
|
|
* Return: code of the operation
|
|
*/
|
|
u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);
|
|
|
|
/**
|
|
* Issue a TPM2_SelfTest command.
|
|
*
|
|
* @dev TPM device
|
|
* @full_test Asking to perform all tests or only the untested ones
|
|
*
|
|
* Return: code of the operation
|
|
*/
|
|
u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);
|
|
|
|
/**
|
|
* Issue a TPM2_Clear command.
|
|
*
|
|
* @dev TPM device
|
|
* @handle Handle
|
|
* @pw Password
|
|
* @pw_sz Length of the password
|
|
*
|
|
* Return: code of the operation
|
|
*/
|
|
u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw,
|
|
const ssize_t pw_sz);
|
|
|
|
/**
|
|
* Issue a TPM_NV_DefineSpace command
|
|
*
|
|
* This allows a space to be defined with given attributes and policy
|
|
*
|
|
* @dev TPM device
|
|
* @space_index index of the area
|
|
* @space_size size of area in bytes
|
|
* @nv_attributes TPM_NV_ATTRIBUTES of the area
|
|
* @nv_policy policy to use
|
|
* @nv_policy_size size of the policy
|
|
* Return: return code of the operation
|
|
*/
|
|
u32 tpm2_nv_define_space(struct udevice *dev, u32 space_index,
|
|
size_t space_size, u32 nv_attributes,
|
|
const u8 *nv_policy, size_t nv_policy_size);
|
|
|
|
/**
|
|
* Issue a TPM2_PCR_Extend command.
|
|
*
|
|
* @dev TPM device
|
|
* @index Index of the PCR
|
|
* @algorithm Algorithm used, defined in 'enum tpm2_algorithms'
|
|
* @digest Value representing the event to be recorded
|
|
* @digest_len len of the hash
|
|
*
|
|
* Return: code of the operation
|
|
*/
|
|
u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm,
|
|
const u8 *digest, u32 digest_len);
|
|
|
|
/**
|
|
* Read data from the secure storage
|
|
*
|
|
* @dev TPM device
|
|
* @index Index of data to read
|
|
* @data Place to put data
|
|
* @count Number of bytes of data
|
|
* Return: code of the operation
|
|
*/
|
|
u32 tpm2_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count);
|
|
|
|
/**
|
|
* Write data to the secure storage
|
|
*
|
|
* @dev TPM device
|
|
* @index Index of data to write
|
|
* @data Data to write
|
|
* @count Number of bytes of data
|
|
* Return: code of the operation
|
|
*/
|
|
u32 tpm2_nv_write_value(struct udevice *dev, u32 index, const void *data,
|
|
u32 count);
|
|
|
|
/**
|
|
* Issue a TPM2_PCR_Read command.
|
|
*
|
|
* @dev TPM device
|
|
* @idx Index of the PCR
|
|
* @idx_min_sz Minimum size in bytes of the pcrSelect array
|
|
* @algorithm Algorithm used, defined in 'enum tpm2_algorithms'
|
|
* @data Output buffer for contents of the named PCR
|
|
* @digest_len len of the data
|
|
* @updates Optional out parameter: number of updates for this PCR
|
|
*
|
|
* Return: code of the operation
|
|
*/
|
|
u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
|
|
u16 algorithm, void *data, u32 digest_len,
|
|
unsigned int *updates);
|
|
|
|
/**
|
|
* Issue a TPM2_GetCapability command. This implementation is limited
|
|
* to query property index that is 4-byte wide.
|
|
*
|
|
* @dev TPM device
|
|
* @capability Partition of capabilities
|
|
* @property Further definition of capability, limited to be 4 bytes wide
|
|
* @buf Output buffer for capability information
|
|
* @prop_count Size of output buffer
|
|
*
|
|
* Return: code of the operation
|
|
*/
|
|
u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
|
|
void *buf, size_t prop_count);
|
|
|
|
/**
|
|
* Issue a TPM2_DictionaryAttackLockReset command.
|
|
*
|
|
* @dev TPM device
|
|
* @pw Password
|
|
* @pw_sz Length of the password
|
|
*
|
|
* Return: code of the operation
|
|
*/
|
|
u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz);
|
|
|
|
/**
|
|
* Issue a TPM2_DictionaryAttackParameters command.
|
|
*
|
|
* @dev TPM device
|
|
* @pw Password
|
|
* @pw_sz Length of the password
|
|
* @max_tries Count of authorizations before lockout
|
|
* @recovery_time Time before decrementation of the failure count
|
|
* @lockout_recovery Time to wait after a lockout
|
|
*
|
|
* Return: code of the operation
|
|
*/
|
|
u32 tpm2_dam_parameters(struct udevice *dev, const char *pw,
|
|
const ssize_t pw_sz, unsigned int max_tries,
|
|
unsigned int recovery_time,
|
|
unsigned int lockout_recovery);
|
|
|
|
/**
|
|
* Issue a TPM2_HierarchyChangeAuth command.
|
|
*
|
|
* @dev TPM device
|
|
* @handle Handle
|
|
* @newpw New password
|
|
* @newpw_sz Length of the new password
|
|
* @oldpw Old password
|
|
* @oldpw_sz Length of the old password
|
|
*
|
|
* Return: code of the operation
|
|
*/
|
|
int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw,
|
|
const ssize_t newpw_sz, const char *oldpw,
|
|
const ssize_t oldpw_sz);
|
|
|
|
/**
|
|
* Issue a TPM_PCR_SetAuthPolicy command.
|
|
*
|
|
* @dev TPM device
|
|
* @pw Platform password
|
|
* @pw_sz Length of the password
|
|
* @index Index of the PCR
|
|
* @digest New key to access the PCR
|
|
*
|
|
* Return: code of the operation
|
|
*/
|
|
u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw,
|
|
const ssize_t pw_sz, u32 index, const char *key);
|
|
|
|
/**
|
|
* Issue a TPM_PCR_SetAuthValue command.
|
|
*
|
|
* @dev TPM device
|
|
* @pw Platform password
|
|
* @pw_sz Length of the password
|
|
* @index Index of the PCR
|
|
* @digest New key to access the PCR
|
|
* @key_sz Length of the new key
|
|
*
|
|
* Return: code of the operation
|
|
*/
|
|
u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw,
|
|
const ssize_t pw_sz, u32 index, const char *key,
|
|
const ssize_t key_sz);
|
|
|
|
/**
|
|
* Issue a TPM2_GetRandom command.
|
|
*
|
|
* @dev TPM device
|
|
* @param data output buffer for the random bytes
|
|
* @param count size of output buffer
|
|
*
|
|
* Return: return code of the operation
|
|
*/
|
|
u32 tpm2_get_random(struct udevice *dev, void *data, u32 count);
|
|
|
|
/**
|
|
* Lock data in the TPM
|
|
*
|
|
* Once locked the data cannot be written until after a reboot
|
|
*
|
|
* @dev TPM device
|
|
* @index Index of data to lock
|
|
* Return: code of the operation
|
|
*/
|
|
u32 tpm2_write_lock(struct udevice *dev, u32 index);
|
|
|
|
/**
|
|
* Disable access to any platform data
|
|
*
|
|
* This can be called to close off access to the firmware data in the data,
|
|
* before calling the kernel.
|
|
*
|
|
* @dev TPM device
|
|
* Return: code of the operation
|
|
*/
|
|
u32 tpm2_disable_platform_hierarchy(struct udevice *dev);
|
|
|
|
/**
|
|
* submit user specified data to the TPM and get response
|
|
*
|
|
* @dev TPM device
|
|
* @sendbuf: Buffer of the data to send
|
|
* @recvbuf: Buffer to save the response to
|
|
* @recv_size: Pointer to the size of the response buffer
|
|
*
|
|
* Return: code of the operation
|
|
*/
|
|
u32 tpm2_submit_command(struct udevice *dev, const u8 *sendbuf,
|
|
u8 *recvbuf, size_t *recv_size);
|
|
|
|
#endif /* __TPM_V2_H */
|