mirror of
https://github.com/AsahiLinux/u-boot
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b2be695166
According to datasheet, the upper four bits are reserved or used for reflecting the ECC status of the accumulated pages. The error bits number for the worst segment of the current page is encoded on lower four bits. Fix it by masking the upper bits. This same issue has been already fixed in the linux kernel by: "mtd: spinand: macronix: Fix ECC Status Read" (sha1: f4cb4d7b46f6409382fd981eec9556e1f3c1dc5d) Apply the same fix in the U-Boot driver. Signed-off-by: Haolin Li <li.haolin@qq.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
202 lines
5.6 KiB
C
202 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 Macronix
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*
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* Author: Boris Brezillon <boris.brezillon@bootlin.com>
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*/
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#ifndef __UBOOT__
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#include <malloc.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#endif
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#include <linux/bug.h>
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#include <linux/mtd/spinand.h>
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#define SPINAND_MFR_MACRONIX 0xC2
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#define MACRONIX_ECCSR_MASK 0x0F
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static SPINAND_OP_VARIANTS(read_cache_variants,
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SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
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static SPINAND_OP_VARIANTS(write_cache_variants,
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SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
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SPINAND_PROG_LOAD(true, 0, NULL, 0));
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static SPINAND_OP_VARIANTS(update_cache_variants,
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SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
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SPINAND_PROG_LOAD(false, 0, NULL, 0));
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static int mx35lfxge4ab_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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return -ERANGE;
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}
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static int mx35lfxge4ab_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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region->offset = 2;
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region->length = mtd->oobsize - 2;
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return 0;
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}
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static const struct mtd_ooblayout_ops mx35lfxge4ab_ooblayout = {
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.ecc = mx35lfxge4ab_ooblayout_ecc,
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.rfree = mx35lfxge4ab_ooblayout_free,
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};
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static int mx35lf1ge4ab_get_eccsr(struct spinand_device *spinand, u8 *eccsr)
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{
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struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x7c, 1),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_DUMMY(1, 1),
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SPI_MEM_OP_DATA_IN(1, eccsr, 1));
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int ret = spi_mem_exec_op(spinand->slave, &op);
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if (ret)
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return ret;
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*eccsr &= MACRONIX_ECCSR_MASK;
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return 0;
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}
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static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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struct nand_device *nand = spinand_to_nand(spinand);
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u8 eccsr;
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switch (status & STATUS_ECC_MASK) {
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case STATUS_ECC_NO_BITFLIPS:
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return 0;
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case STATUS_ECC_UNCOR_ERROR:
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return -EBADMSG;
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case STATUS_ECC_HAS_BITFLIPS:
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/*
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* Let's try to retrieve the real maximum number of bitflips
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* in order to avoid forcing the wear-leveling layer to move
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* data around if it's not necessary.
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*/
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if (mx35lf1ge4ab_get_eccsr(spinand, &eccsr))
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return nand->eccreq.strength;
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if (WARN_ON(eccsr > nand->eccreq.strength || !eccsr))
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return nand->eccreq.strength;
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return eccsr;
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default:
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break;
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}
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return -EINVAL;
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}
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static const struct spinand_info macronix_spinand_table[] = {
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SPINAND_INFO("MX35LF1GE4AB", 0x12,
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NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
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NAND_ECCREQ(4, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
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mx35lf1ge4ab_ecc_get_status)),
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SPINAND_INFO("MX35LF2GE4AB", 0x22,
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NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),
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NAND_ECCREQ(4, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
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SPINAND_INFO("MX35UF4GE4AD", 0xb7,
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NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
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mx35lf1ge4ab_ecc_get_status)),
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SPINAND_INFO("MX35UF2GE4AD", 0xa6,
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NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
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mx35lf1ge4ab_ecc_get_status)),
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SPINAND_INFO("MX35UF2GE4AC", 0xa2,
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NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
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NAND_ECCREQ(4, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
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mx35lf1ge4ab_ecc_get_status)),
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SPINAND_INFO("MX35UF1GE4AD", 0x96,
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NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
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mx35lf1ge4ab_ecc_get_status)),
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SPINAND_INFO("MX35UF1GE4AC", 0x92,
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NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
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NAND_ECCREQ(4, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
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mx35lf1ge4ab_ecc_get_status)),
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};
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static int macronix_spinand_detect(struct spinand_device *spinand)
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{
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u8 *id = spinand->id.data;
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int ret;
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/*
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* Macronix SPI NAND read ID needs a dummy byte, so the first byte in
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* raw_id is garbage.
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*/
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if (id[1] != SPINAND_MFR_MACRONIX)
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return 0;
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ret = spinand_match_and_init(spinand, macronix_spinand_table,
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ARRAY_SIZE(macronix_spinand_table),
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id[2]);
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if (ret)
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return ret;
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return 1;
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}
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static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = {
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.detect = macronix_spinand_detect,
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};
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const struct spinand_manufacturer macronix_spinand_manufacturer = {
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.id = SPINAND_MFR_MACRONIX,
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.name = "Macronix",
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.ops = ¯onix_spinand_manuf_ops,
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};
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