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427f452cb9
On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank
Example:
If GPIO bank have 16 GPIO pins [0-15].
In particular SoC's package case, some GPIO bank can have less GPIO pins:
- [0-10] => 11 pins;
- [2-7] => 6 pins.
Commit dbf928dd26 ("gpio: stm32f7: Add gpio bank holes management")
proposed a first implementation by not counting GPIO "inside" hole. GPIO
are not displaying correctly using gpio or pinmux command when GPIO holes
are located at the beginning of GPIO bank.
To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges
struct to indicate if a GPIO is mapped or not. GPIO uclass offers several
GPIO functions ("input", "output", "unused", "unknown" and "func"), use
"unknown" GPIO function to indicate that a GPIO is not mapped.
stm32_offset_to_index() is no more needed and removed.
This must be reflected using the "gpio" command to indicate to user
that a particular GPIO is not mapped (marked as "unknown") as shown below:
Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins
mapped):
GPIOI0 : unknown
GPIOI1 : unknown
GPIOI2 : analog
GPIOI3 : analog
GPIOI4 : alt function 0 push-pull pull-down
GPIOI5 : alt function 0 push-pull pull-down
GPIOI6 : alt function 0 push-pull pull-down
GPIOI7 : analog
GPIOI8 : unknown
GPIOI9 : unknown
GPIOI10 : unknown
GPIOI11 : unknown
GPIOI12 : unknown
GPIOI13 : unknown
GPIOI14 : unknown
GPIOI15 : unknown
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
84 lines
1.7 KiB
C
84 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
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*/
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#ifndef _STM32_GPIO_PRIV_H_
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#define _STM32_GPIO_PRIV_H_
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enum stm32_gpio_mode {
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STM32_GPIO_MODE_IN = 0,
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STM32_GPIO_MODE_OUT,
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STM32_GPIO_MODE_AF,
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STM32_GPIO_MODE_AN
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};
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enum stm32_gpio_otype {
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STM32_GPIO_OTYPE_PP = 0,
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STM32_GPIO_OTYPE_OD
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};
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enum stm32_gpio_speed {
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STM32_GPIO_SPEED_2M = 0,
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STM32_GPIO_SPEED_25M,
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STM32_GPIO_SPEED_50M,
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STM32_GPIO_SPEED_100M
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};
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enum stm32_gpio_pupd {
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STM32_GPIO_PUPD_NO = 0,
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STM32_GPIO_PUPD_UP,
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STM32_GPIO_PUPD_DOWN
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};
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enum stm32_gpio_af {
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STM32_GPIO_AF0 = 0,
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STM32_GPIO_AF1,
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STM32_GPIO_AF2,
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STM32_GPIO_AF3,
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STM32_GPIO_AF4,
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STM32_GPIO_AF5,
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STM32_GPIO_AF6,
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STM32_GPIO_AF7,
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STM32_GPIO_AF8,
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STM32_GPIO_AF9,
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STM32_GPIO_AF10,
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STM32_GPIO_AF11,
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STM32_GPIO_AF12,
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STM32_GPIO_AF13,
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STM32_GPIO_AF14,
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STM32_GPIO_AF15
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};
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struct stm32_gpio_dsc {
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u8 port;
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u8 pin;
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};
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struct stm32_gpio_ctl {
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enum stm32_gpio_mode mode;
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enum stm32_gpio_otype otype;
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enum stm32_gpio_speed speed;
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enum stm32_gpio_pupd pupd;
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enum stm32_gpio_af af;
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};
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struct stm32_gpio_regs {
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u32 moder; /* GPIO port mode */
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u32 otyper; /* GPIO port output type */
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u32 ospeedr; /* GPIO port output speed */
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u32 pupdr; /* GPIO port pull-up/pull-down */
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u32 idr; /* GPIO port input data */
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u32 odr; /* GPIO port output data */
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u32 bsrr; /* GPIO port bit set/reset */
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u32 lckr; /* GPIO port configuration lock */
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u32 afr[2]; /* GPIO alternate function */
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};
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struct stm32_gpio_priv {
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struct stm32_gpio_regs *regs;
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unsigned int gpio_range;
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};
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#endif /* _STM32_GPIO_PRIV_H_ */
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