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https://github.com/AsahiLinux/u-boot
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7f85330782
The freeze controller is required for FPGA partial reconfig. This node is disable on default. Enable this node via u-boot fdt command when needed. Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com> Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
55 lines
811 B
Text
55 lines
811 B
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* U-Boot additions
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*
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* Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
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*/
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#include "socfpga_agilex-u-boot.dtsi"
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/{
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aliases {
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spi0 = &qspi;
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i2c0 = &i2c1;
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freeze_br0 = &freeze_controller;
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};
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soc {
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freeze_controller: freeze_controller@f9000450 {
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compatible = "altr,freeze-bridge-controller";
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reg = <0xf9000450 0x00000010>;
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status = "disabled";
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};
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};
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memory {
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/* 8GB */
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reg = <0 0x00000000 0 0x80000000>,
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<2 0x80000000 1 0x80000000>;
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};
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};
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&flash0 {
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compatible = "jedec,spi-nor";
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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u-boot,dm-pre-reloc;
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};
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&i2c1 {
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status = "okay";
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};
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&mmc {
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drvsel = <3>;
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smplsel = <0>;
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u-boot,dm-pre-reloc;
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};
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&qspi {
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status = "okay";
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};
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&watchdog0 {
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u-boot,dm-pre-reloc;
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};
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