mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
79 lines
2.1 KiB
C
79 lines
2.1 KiB
C
/*
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* U-boot - main board file
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*
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* Copyright (c) 2005-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <config.h>
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#include <command.h>
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#include <asm/blackfin.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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printf("Board: ADI BF548 EZ-Kit board\n");
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printf(" Support: http://blackfin.uclinux.org/\n");
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
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return gd->bd->bi_memsize;
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}
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int board_early_init_f(void)
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{
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/* Port H: PH8 - PH13 == A4 - A9
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* address lines of the parallel asynchronous memory interface
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*/
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/************************************************
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* configure GPIO *
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* set port H function enable register *
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* configure PH8-PH13 as peripheral (not GPIO) *
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*************************************************/
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bfin_write_PORTH_FER(0x3F03);
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/************************************************
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* set port H MUX to configure PH8-PH13 *
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* 1st Function (MUX = 00) (bits 16-27 == 0) *
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* Set to address signals A4-A9 *
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*************************************************/
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bfin_write_PORTH_MUX(0);
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/************************************************
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* set port H direction register *
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* enable PH8-PH13 as outputs *
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*************************************************/
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bfin_write_PORTH_DIR_SET(0x3F00);
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/* Port I: PI0 - PH14 == A10 - A24
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* address lines of the parallel asynchronous memory interface
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*/
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/************************************************
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* set port I function enable register *
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* configure PI0-PI14 as peripheral (not GPIO) *
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*************************************************/
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bfin_write_PORTI_FER(0x7fff);
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/**************************************************
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* set PORT I MUX to configure PI14-PI0 as *
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* 1st Function (MUX=00) - address signals A10-A24 *
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***************************************************/
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bfin_write_PORTI_MUX(0);
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/****************************************
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* set PORT I direction register *
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* enable PI0 - PI14 as outputs *
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*****************************************/
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bfin_write_PORTI_DIR_SET(0x7fff);
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return 0;
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}
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