mirror of
https://github.com/AsahiLinux/u-boot
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6e7df1d151
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
226 lines
4.6 KiB
ArmAsm
226 lines
4.6 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 MediaTek Inc. All rights reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/cacheops.h>
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#include <asm/addrspace.h>
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#include <asm/mipsmtregs.h>
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#include <asm/cm.h>
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#include "../mt7621.h"
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#include "dram.h"
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#ifndef CFG_SYS_INIT_SP_ADDR
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#define CFG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + \
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CFG_SYS_INIT_SP_OFFSET)
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#endif
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#define SP_ADDR_TEMP 0xbe10dff0
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.macro init_wr sel
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MTC0 zero, CP0_WATCHLO,\sel
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mtc0 t1, CP0_WATCHHI,\sel
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.endm
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.macro setup_stack_gd
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li t0, -16
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PTR_LI t1, CFG_SYS_INIT_SP_ADDR
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and sp, t1, t0 # force 16 byte alignment
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PTR_SUBU \
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sp, sp, GD_SIZE # reserve space for gd
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and sp, sp, t0 # force 16 byte alignment
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move k0, sp # save gd pointer
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#if CONFIG_VAL(SYS_MALLOC_F_LEN) && \
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!CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
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li t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
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PTR_SUBU \
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sp, sp, t2 # reserve space for early malloc
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and sp, sp, t0 # force 16 byte alignment
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#endif
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move fp, sp
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/* Clear gd */
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move t0, k0
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1:
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PTR_S zero, 0(t0)
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PTR_ADDIU t0, PTRSIZE
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blt t0, t1, 1b
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nop
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#if CONFIG_VAL(SYS_MALLOC_F_LEN) && \
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!CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
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PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
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#endif
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.endm
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.set noreorder
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ENTRY(_start)
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b 1f
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mtc0 zero, CP0_COUNT
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/* Stage header required by BootROM */
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.org 0x8
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.word 0 # ep, filled by mkimage
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.word 0 # stage_size, filled by mkimage
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.word 0 # has_stage2
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.word 0 # next_ep
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.word 0 # next_size
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.word 0 # next_offset
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1:
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/* Init CP0 Status */
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mfc0 t0, CP0_STATUS
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and t0, ST0_IMPL
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or t0, ST0_BEV | ST0_ERL
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mtc0 t0, CP0_STATUS
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ehb
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/* Clear Watch Status bits and disable watch exceptions */
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li t1, 0x7 # Clear I, R and W conditions
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init_wr 0
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init_wr 1
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init_wr 2
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init_wr 3
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/* Clear WP, IV and SW interrupts */
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mtc0 zero, CP0_CAUSE
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/* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
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mtc0 zero, CP0_COMPARE
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/* VPE1 goes to wait code directly */
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mfc0 t0, CP0_TCBIND
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andi t0, TCBIND_CURVPE
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bnez t0, launch_vpe_entry
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nop
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/* Core1 goes to specific launch entry */
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PTR_LI t0, KSEG1ADDR(CONFIG_MIPS_CM_BASE)
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lw t1, GCR_Cx_ID(t0)
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bnez t1, launch_core_entry
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nop
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/* MT7530 reset */
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li t0, KSEG1ADDR(SYSCTL_BASE)
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lw t1, SYSCTL_RSTCTL_REG(t0)
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ori t1, MCM_RST
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sw t1, SYSCTL_RSTCTL_REG(t0)
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/* Disable DMA route for PSE SRAM set by BootROM */
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PTR_LI t0, KSEG1ADDR(DMA_CFG_ARB_BASE)
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sw zero, DMA_ROUTE_REG(t0)
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/* Set CPU clock to 500MHz (Required if boot from NAND) */
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li t0, KSEG1ADDR(SYSCTL_BASE)
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lw t1, SYSCTL_CLKCFG0_REG(t0)
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ins t1, zero, 30, 2 # CPU_CLK_SEL
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sw t1, SYSCTL_CLKCFG0_REG(t0)
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/* Set CPU clock divider to 1/1 */
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li t0, KSEG1ADDR(RBUS_BASE)
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li t1, 0x101
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sw t1, RBUS_DYN_CFG0_REG(t0)
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/* (Re-)initialize the SRAM */
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bal mips_sram_init
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nop
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/* Set up temporary stack */
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li sp, SP_ADDR_TEMP
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/* Setup full CPS */
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bal mips_cm_map
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nop
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bal mt7621_cps_init
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nop
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/* Prepare for CPU/DDR initialization binary blob */
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bal prepare_stage_bin
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nop
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/* Call CPU/DDR initialization binary blob */
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li t9, STAGE_LOAD_ADDR
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jalr t9
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nop
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/* Switch CPU PLL source */
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li t0, KSEG1ADDR(SYSCTL_BASE)
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lw t1, SYSCTL_CLKCFG0_REG(t0)
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li t2, 1
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ins t1, t2, CPU_CLK_SEL_S, 2
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sw t1, SYSCTL_CLKCFG0_REG(t0)
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/*
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* Currently SPL is running on locked L2 cache (on KSEG0).
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* To reset the entire cache, we have to writeback SPL to DRAM first.
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* Cache flush won't work here. Use memcpy instead.
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*/
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la a0, __text_start
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move a1, a0
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la a2, __image_copy_end
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sub a2, a2, a1
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li a3, 5
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ins a0, a3, 29, 3 # convert to KSEG1
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bal memcpy
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nop
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/* Disable caches */
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bal mips_cache_disable
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nop
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/* Reset caches */
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bal mips_cache_reset
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nop
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/* Disable SRAM */
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li t0, KSEG1ADDR(FE_BASE)
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li t1, FE_PSE_RESET
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sw t1, FE_RST_GLO_REG(t0)
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/* Clear the .bss section */
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la a0, __bss_start
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la a1, __bss_end
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1: sw zero, 0(a0)
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addiu a0, 4
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ble a0, a1, 1b
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nop
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/* Set up initial stack and global data */
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setup_stack_gd
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#if CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
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/* Set malloc base */
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li t0, (CFG_SYS_INIT_SP_ADDR + 15) & (~15)
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PTR_S t0, GD_MALLOC_BASE(k0) # gd->malloc_base offset
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#endif
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#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_SPL_SERIAL)
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/* Earliest point to set up debug uart */
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bal debug_uart_init
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nop
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#endif
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/* Setup timer */
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bal set_timer_freq_simple
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nop
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/* Bootup secondary CPUs */
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bal secondary_cpu_init
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nop
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move a0, zero # a0 <-- boot_flags = 0
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bal board_init_f
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move ra, zero
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END(_start)
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