mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-14 07:13:03 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
137 lines
2.7 KiB
C
137 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
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*/
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#include <common.h>
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#include <div64.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clk.h>
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#include <asm/io.h>
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static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
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unsigned int get_sys_clk_rate(void)
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{
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if (readl(&clk->sysclk_ctrl) & CLK_SYSCLK_PLL397)
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return RTC_CLK_FREQUENCY * 397;
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else
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return OSC_CLK_FREQUENCY;
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}
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unsigned int get_hclk_pll_rate(void)
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{
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unsigned long long fin, fref, fcco, fout;
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u32 val, m_div, n_div, p_div;
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/*
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* Valid frequency ranges:
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* 1 * 10^6 <= Fin <= 20 * 10^6
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* 1 * 10^6 <= Fref <= 27 * 10^6
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* 156 * 10^6 <= Fcco <= 320 * 10^6
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*/
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fref = fin = get_sys_clk_rate();
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if (fin > 20000000ULL || fin < 1000000ULL)
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return 0;
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val = readl(&clk->hclkpll_ctrl);
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m_div = ((val & CLK_HCLK_PLL_FEEDBACK_DIV_MASK) >> 1) + 1;
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n_div = ((val & CLK_HCLK_PLL_PREDIV_MASK) >> 9) + 1;
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if (val & CLK_HCLK_PLL_DIRECT)
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p_div = 0;
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else
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p_div = ((val & CLK_HCLK_PLL_POSTDIV_MASK) >> 11) + 1;
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p_div = 1 << p_div;
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if (val & CLK_HCLK_PLL_BYPASS) {
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do_div(fin, p_div);
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return fin;
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}
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do_div(fref, n_div);
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if (fref > 27000000ULL || fref < 1000000ULL)
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return 0;
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fcco = fref * m_div;
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fout = fcco;
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if (val & CLK_HCLK_PLL_FEEDBACK)
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fcco *= p_div;
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else
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do_div(fout, p_div);
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if (fcco > 320000000ULL || fcco < 156000000ULL)
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return 0;
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return fout;
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}
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unsigned int get_hclk_clk_div(void)
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{
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u32 val;
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val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK;
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return 1 << val;
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}
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unsigned int get_hclk_clk_rate(void)
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{
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return get_hclk_pll_rate() / get_hclk_clk_div();
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}
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unsigned int get_periph_clk_div(void)
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{
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u32 val;
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val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_PERIPH_DIV_MASK;
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return (val >> 2) + 1;
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}
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unsigned int get_periph_clk_rate(void)
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{
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if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
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return get_sys_clk_rate();
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return get_hclk_pll_rate() / get_periph_clk_div();
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}
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unsigned int get_sdram_clk_rate(void)
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{
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unsigned int src_clk;
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if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
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return get_sys_clk_rate();
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src_clk = get_hclk_pll_rate();
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if (readl(&clk->sdramclk_ctrl) & CLK_SDRAM_DDR_SEL) {
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/* using DDR */
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switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_DDRAM_MASK) {
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case CLK_HCLK_DDRAM_HALF:
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return src_clk/2;
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case CLK_HCLK_DDRAM_NOMINAL:
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return src_clk;
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default:
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return 0;
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}
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} else {
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/* using SDR */
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switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK) {
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case CLK_HCLK_ARM_PLL_DIV_4:
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return src_clk/4;
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case CLK_HCLK_ARM_PLL_DIV_2:
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return src_clk/2;
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case CLK_HCLK_ARM_PLL_DIV_1:
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return src_clk;
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default:
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return 0;
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}
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}
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}
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int get_serial_clock(void)
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{
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return get_periph_clk_rate();
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}
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