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39b32be18c
This patch makes the common 4xx ECC code really usable on 440GP style platforms. Since the IBM DDR controller used on 440GP/GX/EP/GR is not register compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT we need to make some processor dependant defines used later on by the driver. Signed-off-by: Stefan Roese <sr@denx.de>
121 lines
3.5 KiB
C
121 lines
3.5 KiB
C
/*
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* Copyright (c) 2008 Nuovation System Designs, LLC
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* Grant Erickson <gerickson@nuovations.com>
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*
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* (C) Copyright 2005-2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2002
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* Jun Gu, Artesyn Technology, jung@artesyncp.com
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*
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* (C) Copyright 2001
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* Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will abe useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Description:
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* This file implements generic DRAM ECC initialization for
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* PowerPC processors using a SDRAM DDR/DDR2 controller,
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* including the 405EX(r), 440GP/GX/EP/GR, 440SP(E), and
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* 460EX/GT.
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include "ecc.h"
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#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
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#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC)
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/*
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* void ecc_init()
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*
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* Description:
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* This routine initializes a range of DRAM ECC memory with known
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* data and enables ECC checking.
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*
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* TO DO:
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* - Improve performance by utilizing cache.
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* - Further generalize to make usable by other 4xx variants (e.g.
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* 440EPx, et al).
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*
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* Input(s):
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* start - A pointer to the start of memory covered by ECC requiring
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* initialization.
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* size - The size, in bytes, of the memory covered by ECC requiring
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* initialization.
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*
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* Output(s):
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* start - A pointer to the start of memory covered by ECC with
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* CFG_ECC_PATTERN written to all locations and ECC data
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* primed.
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*
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* Returns:
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* N/A
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*/
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void ecc_init(unsigned long * const start, unsigned long size)
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{
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const unsigned long pattern = CFG_ECC_PATTERN;
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unsigned long * const end = (unsigned long * const)((long)start + size);
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unsigned long * current = start;
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unsigned long mcopt1;
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long increment;
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if (start >= end)
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return;
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mfsdram(SDRAM_ECC_CFG, mcopt1);
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/* Enable ECC generation without checking or reporting */
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mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) |
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SDRAM_ECC_CFG_MCHK_GEN));
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increment = sizeof(u32);
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#if defined(CONFIG_440)
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/*
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* Look at the geometry of SDRAM (data width) to determine whether we
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* can skip words when writing.
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*/
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if ((mcopt1 & SDRAM_ECC_CFG_DMWD_MASK) != SDRAM_ECC_CFG_DMWD_32)
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increment = sizeof(u64);
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#endif /* defined(CONFIG_440) */
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while (current < end) {
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*current = pattern;
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current = (unsigned long *)((long)current + increment);
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}
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/* Wait until the writes are finished. */
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sync();
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/* Enable ECC generation with checking and no reporting */
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mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) |
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SDRAM_ECC_CFG_MCHK_CHK));
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}
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#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */
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#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */
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