mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-24 12:03:39 +00:00
6978db36aa
The existing driver is not compatible with the Driver Model. This patch makes the necessary changes while also removing obsolescent calls/properties as follows: - fdtdec_* calls replaced with dev_read_* equivalents; - 'clock-freq-min-max' property replaced by querying the frequency of the source clock 'base_clk'; - The card detect erratum workaround is applied during probe rather than overriding get_cd. The card detect workaround (Microchip ref. DS80000736E, erratum #15) is not always needed and can be disabled using a vendor specific DT property. Signed-off-by: John Robertson <john.robertson@simiatec.com>
93 lines
2 KiB
C
93 lines
2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Support of SDHCI for Microchip PIC32 SoC.
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*
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* Copyright (C) 2015 Microchip Technology Inc.
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* Andrei Pistirica <andrei.pistirica@microchip.com>
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*/
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#include <dm.h>
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#include <sdhci.h>
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#include <clk.h>
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struct pic32_sdhci_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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static int pic32_sdhci_probe(struct udevice *dev)
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{
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct pic32_sdhci_plat *plat = dev_get_platdata(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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struct clk clk;
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ulong clk_rate;
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int ret;
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ret = clk_get_by_name(dev, "base_clk", &clk);
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if (ret)
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return ret;
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clk_rate = clk_get_rate(&clk);
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clk_free(&clk);
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if (IS_ERR_VALUE(clk_rate))
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return clk_rate;
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host->ioaddr = dev_remap_addr(dev);
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if (!host->ioaddr)
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return -EINVAL;
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host->name = dev->name;
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host->quirks = SDHCI_QUIRK_NO_HISPD_BIT;
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host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
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host->max_clk = clk_rate;
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host->mmc = &plat->mmc;
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host->mmc->dev = dev;
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ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
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if (ret)
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return ret;
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host->mmc->priv = host;
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upriv->mmc = host->mmc;
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ret = sdhci_probe(dev);
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if (ret)
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return ret;
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if (!dev_read_bool(dev, "microchip,use-sdcd")) {
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// Use workaround 1 for erratum #15 by default
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u8 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
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ctrl = (ctrl & ~SDHCI_CTRL_CD_TEST_INS) | SDHCI_CTRL_CD_TEST;
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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}
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return 0;
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}
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static int pic32_sdhci_bind(struct udevice *dev)
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{
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struct pic32_sdhci_plat *plat = dev_get_platdata(dev);
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id pic32_sdhci_ids[] = {
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{ .compatible = "microchip,pic32mzda-sdhci" },
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{ }
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};
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U_BOOT_DRIVER(pic32_sdhci_drv) = {
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.name = "pic32_sdhci",
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.id = UCLASS_MMC,
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.of_match = pic32_sdhci_ids,
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.ops = &sdhci_ops,
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.bind = pic32_sdhci_bind,
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.probe = pic32_sdhci_probe,
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.priv_auto_alloc_size = sizeof(struct sdhci_host),
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.platdata_auto_alloc_size = sizeof(struct pic32_sdhci_plat)
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};
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