mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-15 17:28:15 +00:00
105 lines
2.7 KiB
C
105 lines
2.7 KiB
C
/*
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* U-boot - cpu.c CPU specific functions
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*
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* Copyright (c) 2005-2008 Analog Devices Inc.
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/blackfin.h>
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#include <asm/cplb.h>
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#include <asm/mach-common/bits/core.h>
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#include <asm/mach-common/bits/trace.h>
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#include "cpu.h"
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#include "serial.h"
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__attribute__ ((__noreturn__))
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void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
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{
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/* Build a NOP slide over the LDR jump block. Whee! */
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serial_early_puts("NOP Slide\n");
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char nops[0xC];
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memset(nops, 0x00, sizeof(nops));
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extern char _stext_l1;
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memcpy(&_stext_l1 - sizeof(nops), nops, sizeof(nops));
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if (!loaded_from_ldr) {
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/* Relocate sections into L1 if the LDR didn't do it -- don't
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* check length because the linker script does the size
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* checking at build time.
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*/
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serial_early_puts("L1 Relocate\n");
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extern char _stext_l1, _etext_l1, _stext_l1_lma;
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memcpy(&_stext_l1, &_stext_l1_lma, (&_etext_l1 - &_stext_l1));
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extern char _sdata_l1, _edata_l1, _sdata_l1_lma;
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memcpy(&_sdata_l1, &_sdata_l1_lma, (&_edata_l1 - &_sdata_l1));
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}
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#if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
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/* The BF537 bootrom will reset the EBIU_AMGCTL register on us
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* after it has finished loading the LDR. So configure it again.
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*/
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else
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bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
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#endif
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#ifdef CONFIG_DEBUG_DUMP
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/* Turn on hardware trace buffer */
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bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
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#endif
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#ifndef CONFIG_PANIC_HANG
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/* Reset upon a double exception rather than just hanging.
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* Do not do bfin_read on SWRST as that will reset status bits.
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*/
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bfin_write_SWRST(DOUBLE_FAULT);
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#endif
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serial_early_puts("Board init flash\n");
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board_init_f(bootflag);
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}
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int exception_init(void)
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{
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bfin_write_EVT3(trap);
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return 0;
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}
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int irq_init(void)
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{
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#ifdef SIC_IMASK0
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bfin_write_SIC_IMASK0(0);
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bfin_write_SIC_IMASK1(0);
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# ifdef SIC_IMASK2
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bfin_write_SIC_IMASK2(0);
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# endif
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#elif defined(SICA_IMASK0)
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bfin_write_SICA_IMASK0(0);
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bfin_write_SICA_IMASK1(0);
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#else
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bfin_write_SIC_IMASK(0);
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#endif
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bfin_write_EVT2(evt_default); /* NMI */
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bfin_write_EVT5(evt_default); /* hardware error */
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bfin_write_EVT6(evt_default); /* core timer */
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bfin_write_EVT7(evt_default);
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bfin_write_EVT8(evt_default);
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bfin_write_EVT9(evt_default);
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bfin_write_EVT10(evt_default);
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bfin_write_EVT11(evt_default);
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bfin_write_EVT12(evt_default);
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bfin_write_EVT13(evt_default);
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bfin_write_EVT14(evt_default);
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bfin_write_EVT15(evt_default);
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bfin_write_ILAT(0);
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CSYNC();
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/* enable hardware error irq */
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irq_flags = 0x3f;
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local_irq_enable();
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return 0;
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}
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