mirror of
https://github.com/AsahiLinux/u-boot
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3f832699ff
Now that header files no longer include common.h it must be included
first.
Otherwise the build fails with errors like
include/asm/arch/clock.h:43:1: error: unknown type name 'u32'
u32 imx_get_uartclk(void);
Fixes: c3dc39a2f8
("arm: Don't include common.h in header files")
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Reviewed-by: Simon Glass <sjg@chromium.org>
235 lines
5.3 KiB
C
235 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Driver for one wire controller in some i.MX Socs
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*
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* There are currently two silicon variants:
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* V1: i.MX21, i.MX27, i.MX31, i.MX51
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* V2: i.MX25, i.MX35, i.MX50, i.MX53
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* Newer i.MX SoCs such as the i.MX6 do not have one wire controllers.
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*
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* The V1 controller only supports single bit operations.
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* The V2 controller is backwards compatible on the register level but adds
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* byte size operations and a "search ROM accelerator mode"
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*
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* This driver does not currently support the search ROM accelerator
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*
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* Copyright (c) 2018 Flowbird
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* Martin Fuzzey <martin.fuzzey@flowbird.group>
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <w1.h>
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struct mxc_w1_regs {
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u16 control;
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#define MXC_W1_CONTROL_RPP BIT(7)
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#define MXC_W1_CONTROL_PST BIT(6)
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#define MXC_W1_CONTROL_WR(x) BIT(5 - (x))
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#define MXC_W1_CONTROL_RDST BIT(3)
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u16 time_divider;
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u16 reset;
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/* Registers below on V2 silicon only */
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u16 command;
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u16 tx_rx;
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u16 interrupt;
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#define MXC_W1_INTERRUPT_TBE BIT(2)
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#define MXC_W1_INTERRUPT_TSRE BIT(3)
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#define MXC_W1_INTERRUPT_RBF BIT(4)
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#define MXC_W1_INTERRUPT_RSRF BIT(5)
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u16 interrupt_en;
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};
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struct mxc_w1_pdata {
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struct mxc_w1_regs *regs;
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};
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/*
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* this is the low level routine to read/write a bit on the One Wire
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* interface on the hardware. It does write 0 if parameter bit is set
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* to 0, otherwise a write 1/read.
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*/
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static u8 mxc_w1_touch_bit(struct mxc_w1_pdata *pdata, u8 bit)
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{
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u16 *ctrl_addr = &pdata->regs->control;
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u16 mask = MXC_W1_CONTROL_WR(bit);
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unsigned int timeout_cnt = 400; /* Takes max. 120us according to
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* datasheet.
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*/
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writew(mask, ctrl_addr);
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while (timeout_cnt--) {
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if (!(readw(ctrl_addr) & mask))
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break;
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udelay(1);
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}
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return (readw(ctrl_addr) & MXC_W1_CONTROL_RDST) ? 1 : 0;
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}
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static u8 mxc_w1_read_byte(struct udevice *dev)
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{
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struct mxc_w1_pdata *pdata = dev_get_plat(dev);
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struct mxc_w1_regs *regs = pdata->regs;
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u16 status;
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if (dev_get_driver_data(dev) < 2) {
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int i;
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u8 ret = 0;
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for (i = 0; i < 8; i++)
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ret |= (mxc_w1_touch_bit(pdata, 1) << i);
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return ret;
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}
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readw(®s->tx_rx);
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writew(0xFF, ®s->tx_rx);
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do {
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udelay(1); /* Without this bytes are sometimes duplicated... */
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status = readw(®s->interrupt);
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} while (!(status & MXC_W1_INTERRUPT_RBF));
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return (u8)readw(®s->tx_rx);
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}
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static void mxc_w1_write_byte(struct udevice *dev, u8 byte)
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{
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struct mxc_w1_pdata *pdata = dev_get_plat(dev);
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struct mxc_w1_regs *regs = pdata->regs;
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u16 status;
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if (dev_get_driver_data(dev) < 2) {
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int i;
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for (i = 0; i < 8; i++)
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mxc_w1_touch_bit(pdata, (byte >> i) & 0x1);
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return;
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}
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readw(®s->tx_rx);
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writew(byte, ®s->tx_rx);
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do {
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udelay(1);
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status = readw(®s->interrupt);
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} while (!(status & MXC_W1_INTERRUPT_TSRE));
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}
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static bool mxc_w1_reset(struct udevice *dev)
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{
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struct mxc_w1_pdata *pdata = dev_get_plat(dev);
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u16 reg_val;
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writew(MXC_W1_CONTROL_RPP, &pdata->regs->control);
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do {
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reg_val = readw(&pdata->regs->control);
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} while (reg_val & MXC_W1_CONTROL_RPP);
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return !(reg_val & MXC_W1_CONTROL_PST);
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}
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static u8 mxc_w1_triplet(struct udevice *dev, bool bdir)
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{
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struct mxc_w1_pdata *pdata = dev_get_plat(dev);
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u8 id_bit = mxc_w1_touch_bit(pdata, 1);
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u8 comp_bit = mxc_w1_touch_bit(pdata, 1);
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u8 retval;
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if (id_bit && comp_bit)
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return 0x03; /* error */
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if (!id_bit && !comp_bit) {
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/* Both bits are valid, take the direction given */
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retval = bdir ? 0x04 : 0;
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} else {
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/* Only one bit is valid, take that direction */
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bdir = id_bit;
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retval = id_bit ? 0x05 : 0x02;
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}
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mxc_w1_touch_bit(pdata, bdir);
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return retval;
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}
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static int mxc_w1_of_to_plat(struct udevice *dev)
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{
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struct mxc_w1_pdata *pdata = dev_get_plat(dev);
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fdt_addr_t addr;
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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pdata->regs = (struct mxc_w1_regs *)addr;
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return 0;
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};
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static int mxc_w1_probe(struct udevice *dev)
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{
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struct mxc_w1_pdata *pdata = dev_get_plat(dev);
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unsigned int clkrate = mxc_get_clock(MXC_IPG_PERCLK);
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unsigned int clkdiv;
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if (clkrate < 10000000) {
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dev_err(dev, "input clock frequency (%u Hz) too low\n",
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clkrate);
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return -EINVAL;
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}
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clkdiv = clkrate / 1000000;
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clkrate /= clkdiv;
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if (clkrate < 980000 || clkrate > 1020000) {
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dev_err(dev, "Incorrect time base frequency %u Hz\n", clkrate);
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return -EINVAL;
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}
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writew(clkdiv - 1, &pdata->regs->time_divider);
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return 0;
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}
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static const struct w1_ops mxc_w1_ops = {
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.read_byte = mxc_w1_read_byte,
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.reset = mxc_w1_reset,
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.triplet = mxc_w1_triplet,
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.write_byte = mxc_w1_write_byte,
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};
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static const struct udevice_id mxc_w1_id[] = {
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{ .compatible = "fsl,imx21-owire", .data = 1 },
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{ .compatible = "fsl,imx27-owire", .data = 1 },
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{ .compatible = "fsl,imx31-owire", .data = 1 },
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{ .compatible = "fsl,imx51-owire", .data = 1 },
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{ .compatible = "fsl,imx25-owire", .data = 2 },
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{ .compatible = "fsl,imx35-owire", .data = 2 },
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{ .compatible = "fsl,imx50-owire", .data = 2 },
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{ .compatible = "fsl,imx53-owire", .data = 2 },
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{ },
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};
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U_BOOT_DRIVER(mxc_w1_drv) = {
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.id = UCLASS_W1,
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.name = "mxc_w1_drv",
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.of_match = mxc_w1_id,
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.of_to_plat = mxc_w1_of_to_plat,
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.ops = &mxc_w1_ops,
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.plat_auto = sizeof(struct mxc_w1_pdata),
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.probe = mxc_w1_probe,
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};
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