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https://github.com/AsahiLinux/u-boot
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f8c8573b85
This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer]
162 lines
3.6 KiB
C
162 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021
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* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <timer.h>
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#include <dm/device_compat.h>
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#include <asm/io.h>
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#define GPT_CR_EN BIT(0)
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#define GPT_CR_FRR BIT(9)
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#define GPT_CR_EN_24M BIT(10)
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#define GPT_CR_SWR BIT(15)
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#define GPT_PR_PRESCALER24M_MASK 0x0000F000
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#define GPT_PR_PRESCALER24M_SHIFT 12
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#define GPT_PR_PRESCALER24M_MAX (GPT_PR_PRESCALER24M_MASK >> GPT_PR_PRESCALER24M_SHIFT)
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#define GPT_PR_PRESCALER_MASK 0x00000FFF
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#define GPT_PR_PRESCALER_SHIFT 0
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#define GPT_PR_PRESCALER_MAX (GPT_PR_PRESCALER_MASK >> GPT_PR_PRESCALER_SHIFT)
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#define GPT_CLKSRC_IPG_CLK (1 << 6)
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#define GPT_CLKSRC_IPG_CLK_24M (5 << 6)
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/* If CONFIG_SYS_HZ_CLOCK not specified et's default to 3Mhz */
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#ifndef CONFIG_SYS_HZ_CLOCK
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#define CONFIG_SYS_HZ_CLOCK 3000000
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#endif
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struct imx_gpt_timer_regs {
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u32 cr;
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u32 pr;
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u32 sr;
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u32 ir;
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u32 ocr1;
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u32 ocr2;
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u32 ocr3;
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u32 icr1;
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u32 icr2;
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u32 cnt;
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};
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struct imx_gpt_timer_priv {
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struct imx_gpt_timer_regs *base;
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};
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static u64 imx_gpt_timer_get_count(struct udevice *dev)
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{
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struct imx_gpt_timer_priv *priv = dev_get_priv(dev);
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struct imx_gpt_timer_regs *regs = priv->base;
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return timer_conv_64(readl(®s->cnt));
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}
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static int imx_gpt_setup(struct imx_gpt_timer_regs *regs, u32 rate)
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{
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u32 prescaler = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
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/* Reset the timer */
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setbits_le32(®s->cr, GPT_CR_SWR);
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/* Wait for timer to finish reset */
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while (readl(®s->cr) & GPT_CR_SWR)
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;
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if (rate == 24000000UL) {
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/* Set timer frequency if using 24M clock source */
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if (prescaler > GPT_PR_PRESCALER24M_MAX)
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return -EINVAL;
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/* Set 24M prescaler */
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writel((prescaler << GPT_PR_PRESCALER24M_SHIFT), ®s->pr);
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/* Set Oscillator as clock source, enable 24M input and set gpt
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* in free-running mode
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*/
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writel(GPT_CLKSRC_IPG_CLK_24M | GPT_CR_EN_24M | GPT_CR_FRR, ®s->cr);
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} else {
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if (prescaler > GPT_PR_PRESCALER_MAX)
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return -EINVAL;
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/* Set prescaler */
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writel((prescaler << GPT_PR_PRESCALER_SHIFT), ®s->pr);
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/* Set Peripheral as clock source and set gpt in free-running
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* mode
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*/
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writel(GPT_CLKSRC_IPG_CLK | GPT_CR_FRR, ®s->cr);
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}
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/* Start timer */
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setbits_le32(®s->cr, GPT_CR_EN);
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return 0;
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}
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static int imx_gpt_timer_probe(struct udevice *dev)
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{
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct imx_gpt_timer_priv *priv = dev_get_priv(dev);
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struct imx_gpt_timer_regs *regs;
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struct clk clk;
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fdt_addr_t addr;
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u32 clk_rate;
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int ret;
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->base = (struct imx_gpt_timer_regs *)addr;
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regs = priv->base;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&clk);
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if (ret) {
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dev_err(dev, "Failed to enable clock\n");
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return ret;
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}
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/* Get timer clock rate */
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clk_rate = clk_get_rate(&clk);
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if (clk_rate <= 0) {
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dev_err(dev, "Could not get clock rate...\n");
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return -EINVAL;
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}
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ret = imx_gpt_setup(regs, clk_rate);
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if (ret) {
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dev_err(dev, "Could not setup timer\n");
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return ret;
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}
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uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
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return 0;
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}
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static const struct timer_ops imx_gpt_timer_ops = {
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.get_count = imx_gpt_timer_get_count,
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};
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static const struct udevice_id imx_gpt_timer_ids[] = {
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{ .compatible = "fsl,imxrt-gpt" },
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{}
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};
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U_BOOT_DRIVER(imx_gpt_timer) = {
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.name = "imx_gpt_timer",
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.id = UCLASS_TIMER,
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.of_match = imx_gpt_timer_ids,
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.priv_auto = sizeof(struct imx_gpt_timer_priv),
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.probe = imx_gpt_timer_probe,
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.ops = &imx_gpt_timer_ops,
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};
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