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2cc4be280c
Static inline function _debug_uart_init() should avoid calling external (non-inline) functions. Therefore do not call get_ref_clk() in _debug_uart_init() and reimplement its functionality without external function calls. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
349 lines
8.1 KiB
C
349 lines
8.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <serial.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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struct mvebu_plat {
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void __iomem *base;
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ulong tbg_rate;
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u8 tbg_idx;
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};
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/*
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* Register offset
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*/
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#define UART_RX_REG 0x00
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#define UART_TX_REG 0x04
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#define UART_CTRL_REG 0x08
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#define UART_STATUS_REG 0x0c
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#define UART_BAUD_REG 0x10
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#define UART_POSSR_REG 0x14
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#define UART_STATUS_RX_RDY 0x10
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#define UART_STATUS_TX_EMPTY 0x40
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#define UART_STATUS_TXFIFO_FULL 0x800
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#define UART_CTRL_RXFIFO_RESET 0x4000
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#define UART_CTRL_TXFIFO_RESET 0x8000
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static int mvebu_serial_putc(struct udevice *dev, const char ch)
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{
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struct mvebu_plat *plat = dev_get_plat(dev);
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void __iomem *base = plat->base;
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while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
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;
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writel(ch, base + UART_TX_REG);
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return 0;
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}
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static int mvebu_serial_getc(struct udevice *dev)
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{
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struct mvebu_plat *plat = dev_get_plat(dev);
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void __iomem *base = plat->base;
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while (!(readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY))
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;
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return readl(base + UART_RX_REG) & 0xff;
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}
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static int mvebu_serial_pending(struct udevice *dev, bool input)
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{
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struct mvebu_plat *plat = dev_get_plat(dev);
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void __iomem *base = plat->base;
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if (input) {
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if (readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY)
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return 1;
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} else {
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if (!(readl(base + UART_STATUS_REG) & UART_STATUS_TX_EMPTY))
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return 1;
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}
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return 0;
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}
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static int mvebu_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct mvebu_plat *plat = dev_get_plat(dev);
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void __iomem *base = plat->base;
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u32 divider, d1, d2;
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u32 oversampling;
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/*
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* Calculate divider
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* baudrate = clock / 16 / divider
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*/
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d1 = d2 = 1;
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divider = DIV_ROUND_CLOSEST(plat->tbg_rate, baudrate * 16 * d1 * d2);
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/*
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* Set Programmable Oversampling Stack to 0,
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* UART defaults to 16x scheme
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*/
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oversampling = 0;
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if (divider < 1)
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divider = 1;
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else if (divider > 1023) {
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/*
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* If divider is too high for selected baudrate then set
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* divider d1 to the maximal value 6.
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*/
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d1 = 6;
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divider = DIV_ROUND_CLOSEST(plat->tbg_rate,
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baudrate * 16 * d1 * d2);
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if (divider < 1)
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divider = 1;
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else if (divider > 1023) {
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/*
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* If divider is still too high then set also divider
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* d2 to the maximal value 6.
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*/
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d2 = 6;
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divider = DIV_ROUND_CLOSEST(plat->tbg_rate,
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baudrate * 16 * d1 * d2);
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if (divider < 1)
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divider = 1;
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else if (divider > 1023) {
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/*
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* And if divider is still to high then
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* use oversampling with maximal factor 63.
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*/
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oversampling = (63 << 0) | (63 << 8) |
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(63 << 16) | (63 << 24);
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divider = DIV_ROUND_CLOSEST(plat->tbg_rate,
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baudrate * 63 * d1 * d2);
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if (divider < 1)
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divider = 1;
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else if (divider > 1023)
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divider = 1023;
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}
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}
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}
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divider |= BIT(19); /* Do not use XTAL as a base clock */
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divider |= d1 << 15; /* Set d1 divider */
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divider |= d2 << 12; /* Set d2 divider */
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divider |= plat->tbg_idx << 10; /* Use selected TBG as a base clock */
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while (!(readl(base + UART_STATUS_REG) & UART_STATUS_TX_EMPTY))
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;
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writel(divider, base + UART_BAUD_REG);
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writel(oversampling, base + UART_POSSR_REG);
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return 0;
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}
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static int mvebu_serial_probe(struct udevice *dev)
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{
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struct mvebu_plat *plat = dev_get_plat(dev);
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void __iomem *base = plat->base;
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struct udevice *nb_clk;
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ofnode nb_clk_node;
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int i, res;
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nb_clk_node = ofnode_by_compatible(ofnode_null(),
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"marvell,armada-3700-periph-clock-nb");
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if (!ofnode_valid(nb_clk_node)) {
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printf("%s: NB periph clock node not available\n", __func__);
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return -ENODEV;
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}
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res = device_get_global_by_ofnode(nb_clk_node, &nb_clk);
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if (res) {
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printf("%s: Cannot get NB periph clock\n", __func__);
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return res;
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}
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/*
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* Choose the TBG clock with lowest frequency which allows to configure
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* UART also at lower baudrates.
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*/
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for (i = 0; i < 4; i++) {
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struct clk clk;
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ulong rate;
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res = clk_get_by_index_nodev(nb_clk_node, i, &clk);
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if (res) {
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printf("%s: Cannot get TBG clock %i: %i\n", __func__,
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i, res);
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return -ENODEV;
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}
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rate = clk_get_rate(&clk);
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if (!rate || IS_ERR_VALUE(rate)) {
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printf("%s: Cannot get rate for TBG clock %i\n",
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__func__, i);
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return -EINVAL;
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}
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if (!i || plat->tbg_rate > rate) {
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plat->tbg_rate = rate;
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plat->tbg_idx = i;
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}
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}
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/* reset FIFOs */
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writel(UART_CTRL_RXFIFO_RESET | UART_CTRL_TXFIFO_RESET,
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base + UART_CTRL_REG);
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/* No Parity, 1 Stop */
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writel(0, base + UART_CTRL_REG);
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return 0;
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}
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static int mvebu_serial_remove(struct udevice *dev)
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{
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struct mvebu_plat *plat = dev_get_plat(dev);
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void __iomem *base = plat->base;
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ulong new_parent_rate, parent_rate;
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u32 new_divider, divider;
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u32 new_oversampling;
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u32 oversampling;
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u32 d1, d2;
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/*
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* Switch UART base clock back to XTAL because older Linux kernel
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* expects it. Otherwise it does not calculate UART divisor correctly
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* and therefore UART does not work in kernel.
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*/
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divider = readl(base + UART_BAUD_REG);
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if (!(divider & BIT(19))) /* UART already uses XTAL */
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return 0;
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/* Read current divisors settings */
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d1 = (divider >> 15) & 7;
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d2 = (divider >> 12) & 7;
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parent_rate = plat->tbg_rate;
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divider &= 1023;
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oversampling = readl(base + UART_POSSR_REG) & 63;
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if (!oversampling)
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oversampling = 16;
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/* Calculate new divisor against XTAL clock without changing baudrate */
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new_oversampling = 0;
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new_parent_rate = get_ref_clk() * 1000000;
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new_divider = DIV_ROUND_CLOSEST(new_parent_rate * divider * d1 * d2 *
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oversampling, parent_rate * 16);
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/*
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* UART does not work reliably when XTAL divisor is smaller than 4.
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* In this case we do not switch UART parent to XTAL. User either
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* configured unsupported settings or has newer kernel with patches
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* which allow usage of non-XTAL clock as a parent clock.
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*/
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if (new_divider < 4)
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return 0;
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/*
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* If new divisor is larger than maximal supported, try to switch
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* from default x16 scheme to oversampling with maximal factor 63.
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*/
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if (new_divider > 1023) {
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new_oversampling = 63;
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new_divider = DIV_ROUND_CLOSEST(new_parent_rate * divider * d1 *
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d2 * oversampling,
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parent_rate * new_oversampling);
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if (new_divider < 4 || new_divider > 1023)
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return 0;
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}
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while (!(readl(base + UART_STATUS_REG) & UART_STATUS_TX_EMPTY))
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;
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writel(new_divider, base + UART_BAUD_REG);
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writel(new_oversampling, base + UART_POSSR_REG);
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return 0;
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}
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static int mvebu_serial_of_to_plat(struct udevice *dev)
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{
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struct mvebu_plat *plat = dev_get_plat(dev);
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plat->base = dev_read_addr_ptr(dev);
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return 0;
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}
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static const struct dm_serial_ops mvebu_serial_ops = {
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.putc = mvebu_serial_putc,
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.pending = mvebu_serial_pending,
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.getc = mvebu_serial_getc,
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.setbrg = mvebu_serial_setbrg,
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};
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static const struct udevice_id mvebu_serial_ids[] = {
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{ .compatible = "marvell,armada-3700-uart" },
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{ }
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};
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U_BOOT_DRIVER(serial_mvebu) = {
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.name = "serial_mvebu",
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.id = UCLASS_SERIAL,
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.of_match = mvebu_serial_ids,
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.of_to_plat = mvebu_serial_of_to_plat,
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.plat_auto = sizeof(struct mvebu_plat),
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.probe = mvebu_serial_probe,
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.remove = mvebu_serial_remove,
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.flags = DM_FLAG_OS_PREPARE,
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.ops = &mvebu_serial_ops,
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};
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#ifdef CONFIG_DEBUG_MVEBU_A3700_UART
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#include <debug_uart.h>
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#include <mach/soc.h>
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static inline void _debug_uart_init(void)
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{
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void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
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u32 parent_rate, divider;
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/* reset FIFOs */
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writel(UART_CTRL_RXFIFO_RESET | UART_CTRL_TXFIFO_RESET,
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base + UART_CTRL_REG);
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/* No Parity, 1 Stop */
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writel(0, base + UART_CTRL_REG);
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/*
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* Calculate divider
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* baudrate = clock / 16 / divider
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*/
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parent_rate = (readl(MVEBU_REGISTER(0x13808)) & BIT(9)) ?
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40000000 : 25000000;
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divider = DIV_ROUND_CLOSEST(parent_rate, CONFIG_BAUDRATE * 16);
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writel(divider, base + UART_BAUD_REG);
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/*
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* Set Programmable Oversampling Stack to 0,
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* UART defaults to 16x scheme
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*/
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writel(0, base + UART_POSSR_REG);
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}
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static inline void _debug_uart_putc(int ch)
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{
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void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
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while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
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;
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writel(ch, base + UART_TX_REG);
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}
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DEBUG_UART_FUNCS
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#endif
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