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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
243 lines
5.6 KiB
C
243 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <dm.h>
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#include <div64.h>
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#include <errno.h>
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#include <serial.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <dm/pinctrl.h>
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#include <linux/bitops.h>
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#include <mach/ar71xx_regs.h>
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#define AR933X_UART_DATA_REG 0x00
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#define AR933X_UART_CS_REG 0x04
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#define AR933X_UART_CLK_REG 0x08
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#define AR933X_UART_DATA_TX_RX_MASK 0xff
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#define AR933X_UART_DATA_RX_CSR BIT(8)
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#define AR933X_UART_DATA_TX_CSR BIT(9)
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#define AR933X_UART_CS_IF_MODE_S 2
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#define AR933X_UART_CS_IF_MODE_M 0x3
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#define AR933X_UART_CS_IF_MODE_DTE 1
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#define AR933X_UART_CS_IF_MODE_DCE 2
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#define AR933X_UART_CS_TX_RDY_ORIDE BIT(7)
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#define AR933X_UART_CS_RX_RDY_ORIDE BIT(8)
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#define AR933X_UART_CLK_STEP_M 0xffff
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#define AR933X_UART_CLK_SCALE_M 0xfff
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#define AR933X_UART_CLK_SCALE_S 16
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#define AR933X_UART_CLK_STEP_S 0
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struct ar933x_serial_priv {
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void __iomem *regs;
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};
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/*
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* Baudrate algorithm come from Linux/drivers/tty/serial/ar933x_uart.c
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* baudrate = (clk / (scale + 1)) * (step * (1 / 2^17))
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*/
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static u32 ar933x_serial_get_baud(u32 clk, u32 scale, u32 step)
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{
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u64 t;
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u32 div;
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div = (2 << 16) * (scale + 1);
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t = clk;
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t *= step;
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t += (div / 2);
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do_div(t, div);
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return t;
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}
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static void ar933x_serial_get_scale_step(u32 clk, u32 baud,
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u32 *scale, u32 *step)
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{
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u32 tscale, baudrate;
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long min_diff;
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*scale = 0;
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*step = 0;
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min_diff = baud;
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for (tscale = 0; tscale < AR933X_UART_CLK_SCALE_M; tscale++) {
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u64 tstep;
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int diff;
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tstep = baud * (tscale + 1);
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tstep *= (2 << 16);
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do_div(tstep, clk);
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if (tstep > AR933X_UART_CLK_STEP_M)
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break;
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baudrate = ar933x_serial_get_baud(clk, tscale, tstep);
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diff = abs(baudrate - baud);
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if (diff < min_diff) {
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min_diff = diff;
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*scale = tscale;
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*step = tstep;
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}
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}
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}
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static int ar933x_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct ar933x_serial_priv *priv = dev_get_priv(dev);
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u32 val, scale, step;
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val = get_serial_clock();
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ar933x_serial_get_scale_step(val, baudrate, &scale, &step);
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val = (scale & AR933X_UART_CLK_SCALE_M)
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<< AR933X_UART_CLK_SCALE_S;
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val |= (step & AR933X_UART_CLK_STEP_M)
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<< AR933X_UART_CLK_STEP_S;
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writel(val, priv->regs + AR933X_UART_CLK_REG);
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return 0;
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}
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static int ar933x_serial_putc(struct udevice *dev, const char c)
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{
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struct ar933x_serial_priv *priv = dev_get_priv(dev);
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u32 data;
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data = readl(priv->regs + AR933X_UART_DATA_REG);
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if (!(data & AR933X_UART_DATA_TX_CSR))
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return -EAGAIN;
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data = (u32)c | AR933X_UART_DATA_TX_CSR;
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writel(data, priv->regs + AR933X_UART_DATA_REG);
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return 0;
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}
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static int ar933x_serial_getc(struct udevice *dev)
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{
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struct ar933x_serial_priv *priv = dev_get_priv(dev);
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u32 data;
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data = readl(priv->regs + AR933X_UART_DATA_REG);
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if (!(data & AR933X_UART_DATA_RX_CSR))
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return -EAGAIN;
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writel(AR933X_UART_DATA_RX_CSR, priv->regs + AR933X_UART_DATA_REG);
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return data & AR933X_UART_DATA_TX_RX_MASK;
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}
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static int ar933x_serial_pending(struct udevice *dev, bool input)
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{
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struct ar933x_serial_priv *priv = dev_get_priv(dev);
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u32 data;
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data = readl(priv->regs + AR933X_UART_DATA_REG);
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if (input)
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return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0;
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else
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return (data & AR933X_UART_DATA_TX_CSR) ? 0 : 1;
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}
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static int ar933x_serial_probe(struct udevice *dev)
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{
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struct ar933x_serial_priv *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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u32 val;
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->regs = map_physmem(addr, AR933X_UART_SIZE,
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MAP_NOCACHE);
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/*
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* UART controller configuration:
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* - no DMA
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* - no interrupt
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* - DCE mode
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* - no flow control
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* - set RX ready oride
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* - set TX ready oride
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*/
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val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) |
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AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE;
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writel(val, priv->regs + AR933X_UART_CS_REG);
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return 0;
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}
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static const struct dm_serial_ops ar933x_serial_ops = {
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.putc = ar933x_serial_putc,
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.pending = ar933x_serial_pending,
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.getc = ar933x_serial_getc,
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.setbrg = ar933x_serial_setbrg,
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};
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static const struct udevice_id ar933x_serial_ids[] = {
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{ .compatible = "qca,ar9330-uart" },
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{ }
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};
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U_BOOT_DRIVER(serial_ar933x) = {
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.name = "serial_ar933x",
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.id = UCLASS_SERIAL,
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.of_match = ar933x_serial_ids,
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.priv_auto = sizeof(struct ar933x_serial_priv),
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.probe = ar933x_serial_probe,
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.ops = &ar933x_serial_ops,
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};
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#ifdef CONFIG_DEBUG_UART_AR933X
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#include <debug_uart.h>
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static inline void _debug_uart_init(void)
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{
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void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE;
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u32 val, scale, step;
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/*
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* UART controller configuration:
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* - no DMA
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* - no interrupt
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* - DCE mode
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* - no flow control
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* - set RX ready oride
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* - set TX ready oride
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*/
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val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) |
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AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE;
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writel(val, regs + AR933X_UART_CS_REG);
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ar933x_serial_get_scale_step(CONFIG_DEBUG_UART_CLOCK,
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CONFIG_BAUDRATE, &scale, &step);
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val = (scale & AR933X_UART_CLK_SCALE_M)
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<< AR933X_UART_CLK_SCALE_S;
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val |= (step & AR933X_UART_CLK_STEP_M)
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<< AR933X_UART_CLK_STEP_S;
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writel(val, regs + AR933X_UART_CLK_REG);
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}
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static inline void _debug_uart_putc(int c)
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{
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void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE;
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u32 data;
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do {
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data = readl(regs + AR933X_UART_DATA_REG);
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} while (!(data & AR933X_UART_DATA_TX_CSR));
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data = (u32)c | AR933X_UART_DATA_TX_CSR;
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writel(data, regs + AR933X_UART_DATA_REG);
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}
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DEBUG_UART_FUNCS
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#endif
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