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https://github.com/AsahiLinux/u-boot
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401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
338 lines
7.4 KiB
C
338 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* Modified to support C structur SoC access by
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* Andreas Bießmann <biessmann@corscience.de>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <malloc.h>
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#include <watchdog.h>
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#include <serial.h>
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#include <debug_uart.h>
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#include <asm/global_data.h>
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#include <linux/compiler.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#ifdef CONFIG_DM_SERIAL
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#include <asm/arch/atmel_serial.h>
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#endif
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#include <asm/arch/clk.h>
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#include <asm/arch/hardware.h>
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#include "atmel_usart.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_DM_SERIAL
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static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id,
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int baudrate)
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{
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unsigned long divisor;
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unsigned long usart_hz;
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/*
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* Master Clock
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* Baud Rate = --------------
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* 16 * CD
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*/
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usart_hz = get_usart_clk_rate(id);
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divisor = (usart_hz / 16 + baudrate / 2) / baudrate;
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writel(USART3_BF(CD, divisor), &usart->brgr);
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}
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static void atmel_serial_init_internal(atmel_usart3_t *usart)
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{
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/*
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* Just in case: drain transmitter register
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* 1000us is enough for baudrate >= 9600
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*/
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if (!(readl(&usart->csr) & USART3_BIT(TXEMPTY)))
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__udelay(1000);
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writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
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}
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static void atmel_serial_activate(atmel_usart3_t *usart)
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{
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writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
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| USART3_BF(USCLKS, USART3_USCLKS_MCK)
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| USART3_BF(CHRL, USART3_CHRL_8)
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| USART3_BF(PAR, USART3_PAR_NONE)
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| USART3_BF(NBSTOP, USART3_NBSTOP_1)),
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&usart->mr);
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writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
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/* 100us is enough for the new settings to be settled */
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__udelay(100);
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}
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static void atmel_serial_setbrg(void)
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{
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atmel_serial_setbrg_internal((atmel_usart3_t *)CONFIG_USART_BASE,
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CONFIG_USART_ID, gd->baudrate);
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}
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static int atmel_serial_init(void)
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{
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atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
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atmel_serial_init_internal(usart);
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serial_setbrg();
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atmel_serial_activate(usart);
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return 0;
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}
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static void atmel_serial_putc(char c)
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{
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atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
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if (c == '\n')
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serial_putc('\r');
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while (!(readl(&usart->csr) & USART3_BIT(TXRDY)));
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writel(c, &usart->thr);
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}
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static int atmel_serial_getc(void)
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{
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atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
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while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
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WATCHDOG_RESET();
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return readl(&usart->rhr);
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}
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static int atmel_serial_tstc(void)
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{
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atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
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return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
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}
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static struct serial_device atmel_serial_drv = {
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.name = "atmel_serial",
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.start = atmel_serial_init,
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.stop = NULL,
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.setbrg = atmel_serial_setbrg,
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.putc = atmel_serial_putc,
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.puts = default_serial_puts,
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.getc = atmel_serial_getc,
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.tstc = atmel_serial_tstc,
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};
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void atmel_serial_initialize(void)
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{
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serial_register(&atmel_serial_drv);
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}
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__weak struct serial_device *default_serial_console(void)
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{
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return &atmel_serial_drv;
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}
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#endif
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#ifdef CONFIG_DM_SERIAL
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enum serial_clk_type {
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CLK_TYPE_NORMAL = 0,
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CLK_TYPE_DBGU,
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};
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struct atmel_serial_priv {
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atmel_usart3_t *usart;
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ulong usart_clk_rate;
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};
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static void _atmel_serial_set_brg(atmel_usart3_t *usart,
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ulong usart_clk_rate, int baudrate)
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{
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unsigned long divisor;
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divisor = (usart_clk_rate / 16 + baudrate / 2) / baudrate;
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writel(USART3_BF(CD, divisor), &usart->brgr);
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}
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void _atmel_serial_init(atmel_usart3_t *usart,
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ulong usart_clk_rate, int baudrate)
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{
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writel(USART3_BIT(RXDIS) | USART3_BIT(TXDIS), &usart->cr);
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writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) |
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USART3_BF(USCLKS, USART3_USCLKS_MCK) |
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USART3_BF(CHRL, USART3_CHRL_8) |
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USART3_BF(PAR, USART3_PAR_NONE) |
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USART3_BF(NBSTOP, USART3_NBSTOP_1)), &usart->mr);
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_atmel_serial_set_brg(usart, usart_clk_rate, baudrate);
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writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
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writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
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}
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int atmel_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct atmel_serial_priv *priv = dev_get_priv(dev);
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_atmel_serial_set_brg(priv->usart, priv->usart_clk_rate, baudrate);
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return 0;
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}
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static int atmel_serial_getc(struct udevice *dev)
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{
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struct atmel_serial_priv *priv = dev_get_priv(dev);
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if (!(readl(&priv->usart->csr) & USART3_BIT(RXRDY)))
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return -EAGAIN;
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return readl(&priv->usart->rhr);
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}
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static int atmel_serial_putc(struct udevice *dev, const char ch)
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{
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struct atmel_serial_priv *priv = dev_get_priv(dev);
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if (!(readl(&priv->usart->csr) & USART3_BIT(TXRDY)))
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return -EAGAIN;
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writel(ch, &priv->usart->thr);
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return 0;
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}
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static int atmel_serial_pending(struct udevice *dev, bool input)
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{
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struct atmel_serial_priv *priv = dev_get_priv(dev);
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uint32_t csr = readl(&priv->usart->csr);
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if (input)
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return csr & USART3_BIT(RXRDY) ? 1 : 0;
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else
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return csr & USART3_BIT(TXEMPTY) ? 0 : 1;
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}
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static const struct dm_serial_ops atmel_serial_ops = {
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.putc = atmel_serial_putc,
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.pending = atmel_serial_pending,
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.getc = atmel_serial_getc,
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.setbrg = atmel_serial_setbrg,
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};
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#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK)
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static int atmel_serial_enable_clk(struct udevice *dev)
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{
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struct atmel_serial_priv *priv = dev_get_priv(dev);
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/* Use fixed clock value in SPL */
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priv->usart_clk_rate = CONFIG_SPL_UART_CLOCK;
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return 0;
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}
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#else
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static int atmel_serial_enable_clk(struct udevice *dev)
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{
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struct atmel_serial_priv *priv = dev_get_priv(dev);
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struct clk clk;
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ulong clk_rate;
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int ret;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return -EINVAL;
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if (dev_get_driver_data(dev) == CLK_TYPE_NORMAL) {
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ret = clk_enable(&clk);
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if (ret)
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return ret;
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}
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clk_rate = clk_get_rate(&clk);
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if (!clk_rate)
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return -EINVAL;
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priv->usart_clk_rate = clk_rate;
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clk_free(&clk);
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return 0;
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}
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#endif
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static int atmel_serial_probe(struct udevice *dev)
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{
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struct atmel_serial_plat *plat = dev_get_plat(dev);
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struct atmel_serial_priv *priv = dev_get_priv(dev);
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int ret;
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#if CONFIG_IS_ENABLED(OF_CONTROL)
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fdt_addr_t addr_base;
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addr_base = dev_read_addr(dev);
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if (addr_base == FDT_ADDR_T_NONE)
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return -ENODEV;
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plat->base_addr = (uint32_t)addr_base;
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#endif
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priv->usart = (atmel_usart3_t *)plat->base_addr;
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ret = atmel_serial_enable_clk(dev);
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if (ret)
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return ret;
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_atmel_serial_init(priv->usart, priv->usart_clk_rate, gd->baudrate);
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return 0;
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}
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#if CONFIG_IS_ENABLED(OF_CONTROL)
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static const struct udevice_id atmel_serial_ids[] = {
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{
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.compatible = "atmel,at91sam9260-dbgu",
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.data = CLK_TYPE_DBGU,
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},
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{
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.compatible = "atmel,at91sam9260-usart",
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.data = CLK_TYPE_NORMAL,
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},
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{ }
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};
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#endif
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U_BOOT_DRIVER(serial_atmel) = {
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.name = "serial_atmel",
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.id = UCLASS_SERIAL,
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#if CONFIG_IS_ENABLED(OF_CONTROL)
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.of_match = atmel_serial_ids,
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.plat_auto = sizeof(struct atmel_serial_plat),
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#endif
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.probe = atmel_serial_probe,
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.ops = &atmel_serial_ops,
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#if !CONFIG_IS_ENABLED(OF_CONTROL)
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.flags = DM_FLAG_PRE_RELOC,
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#endif
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.priv_auto = sizeof(struct atmel_serial_priv),
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};
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#endif
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#ifdef CONFIG_DEBUG_UART_ATMEL
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static inline void _debug_uart_init(void)
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{
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atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
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_atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
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}
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static inline void _debug_uart_putc(int ch)
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{
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atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
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while (!(readl(&usart->csr) & USART3_BIT(TXRDY)))
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;
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writel(ch, &usart->thr);
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}
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DEBUG_UART_FUNCS
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#endif
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