mirror of
https://github.com/AsahiLinux/u-boot
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08ea87a6de
On reset, the RTC loads the 2000-01-01 date with a wrong day of the week (Sunday instead of Saturday). Signed-off-by: Dario Binacchi <dariobin@libero.it> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210602203805.11494-9-dariobin@libero.it
444 lines
11 KiB
C
444 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2011 DENX Software Engineering GmbH
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* Heiko Schocher <hs@denx.de>
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* Copyright (C) 2021 Dario Binacchi <dariobin@libero.it>
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*/
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#include <common.h>
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#include <command.h>
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#include <dm.h>
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#include <clk.h>
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#include <log.h>
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#include <rtc.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <linux/delay.h>
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/* RTC registers */
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#define OMAP_RTC_SECONDS_REG 0x00
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#define OMAP_RTC_MINUTES_REG 0x04
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#define OMAP_RTC_HOURS_REG 0x08
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#define OMAP_RTC_DAYS_REG 0x0C
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#define OMAP_RTC_MONTHS_REG 0x10
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#define OMAP_RTC_YEARS_REG 0x14
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#define OMAP_RTC_WEEKS_REG 0x18
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#define OMAP_RTC_CTRL_REG 0x40
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#define OMAP_RTC_STATUS_REG 0x44
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#define OMAP_RTC_INTERRUPTS_REG 0x48
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#define OMAP_RTC_OSC_REG 0x54
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#define OMAP_RTC_SCRATCH0_REG 0x60
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#define OMAP_RTC_SCRATCH1_REG 0x64
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#define OMAP_RTC_SCRATCH2_REG 0x68
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#define OMAP_RTC_KICK0_REG 0x6c
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#define OMAP_RTC_KICK1_REG 0x70
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#define OMAP_RTC_PMIC_REG 0x98
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/* OMAP_RTC_CTRL_REG bit fields: */
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#define OMAP_RTC_CTRL_SPLIT BIT(7)
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#define OMAP_RTC_CTRL_DISABLE BIT(6)
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#define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5)
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#define OMAP_RTC_CTRL_TEST BIT(4)
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#define OMAP_RTC_CTRL_MODE_12_24 BIT(3)
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#define OMAP_RTC_CTRL_AUTO_COMP BIT(2)
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#define OMAP_RTC_CTRL_ROUND_30S BIT(1)
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#define OMAP_RTC_CTRL_STOP BIT(0)
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/* OMAP_RTC_STATUS_REG bit fields */
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#define OMAP_RTC_STATUS_POWER_UP BIT(7)
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#define OMAP_RTC_STATUS_ALARM2 BIT(7)
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#define OMAP_RTC_STATUS_ALARM BIT(6)
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#define OMAP_RTC_STATUS_1D_EVENT BIT(5)
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#define OMAP_RTC_STATUS_1H_EVENT BIT(4)
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#define OMAP_RTC_STATUS_1M_EVENT BIT(3)
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#define OMAP_RTC_STATUS_1S_EVENT BIT(2)
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#define OMAP_RTC_STATUS_RUN BIT(1)
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#define OMAP_RTC_STATUS_BUSY BIT(0)
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/* OMAP_RTC_OSC_REG bit fields */
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#define OMAP_RTC_OSC_32KCLK_EN BIT(6)
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#define OMAP_RTC_OSC_SEL_32KCLK_SRC BIT(3)
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#define OMAP_RTC_OSC_OSC32K_GZ_DISABLE BIT(4)
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/* OMAP_RTC_KICKER values */
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#define OMAP_RTC_KICK0_VALUE 0x83e70b13
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#define OMAP_RTC_KICK1_VALUE 0x95a4f1e0
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struct omap_rtc_device_type {
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bool has_32kclk_en;
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bool has_irqwakeen;
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bool has_pmic_mode;
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bool has_power_up_reset;
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};
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struct omap_rtc_priv {
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fdt_addr_t base;
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u8 max_reg;
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struct udevice *dev;
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struct clk clk;
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bool has_ext_clk;
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const struct omap_rtc_device_type *type;
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};
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static inline u8 omap_rtc_readb(struct omap_rtc_priv *priv, unsigned int reg)
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{
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return readb(priv->base + reg);
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}
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static inline u32 omap_rtc_readl(struct omap_rtc_priv *priv, unsigned int reg)
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{
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return readl(priv->base + reg);
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}
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static inline void omap_rtc_writeb(struct omap_rtc_priv *priv, unsigned int reg,
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u8 val)
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{
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writeb(val, priv->base + reg);
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}
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static inline void omap_rtc_writel(struct omap_rtc_priv *priv, unsigned int reg,
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u32 val)
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{
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writel(val, priv->base + reg);
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}
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static inline void omap_rtc_unlock(struct omap_rtc_priv *priv)
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{
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omap_rtc_writel(priv, OMAP_RTC_KICK0_REG, OMAP_RTC_KICK0_VALUE);
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omap_rtc_writel(priv, OMAP_RTC_KICK1_REG, OMAP_RTC_KICK1_VALUE);
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}
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static inline void omap_rtc_lock(struct omap_rtc_priv *priv)
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{
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omap_rtc_writel(priv, OMAP_RTC_KICK0_REG, 0);
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omap_rtc_writel(priv, OMAP_RTC_KICK1_REG, 0);
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}
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static int omap_rtc_wait_not_busy(struct omap_rtc_priv *priv)
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{
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int count;
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u8 status;
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status = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG);
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if ((status & OMAP_RTC_STATUS_RUN) != OMAP_RTC_STATUS_RUN) {
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printf("RTC doesn't run\n");
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return -1;
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}
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/* BUSY may stay active for 1/32768 second (~30 usec) */
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for (count = 0; count < 50; count++) {
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if (!(status & OMAP_RTC_STATUS_BUSY))
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break;
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udelay(1);
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status = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG);
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}
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/* now we have ~15 usec to read/write various registers */
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return 0;
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}
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static int omap_rtc_reset(struct udevice *dev)
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{
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struct omap_rtc_priv *priv = dev_get_priv(dev);
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/* run RTC counter */
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omap_rtc_writeb(priv, OMAP_RTC_CTRL_REG, 0x01);
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return 0;
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}
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static int omap_rtc_set(struct udevice *dev, const struct rtc_time *tm)
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{
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struct omap_rtc_priv *priv = dev_get_priv(dev);
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int ret;
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ret = omap_rtc_wait_not_busy(priv);
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if (ret)
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return ret;
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omap_rtc_unlock(priv);
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omap_rtc_writeb(priv, OMAP_RTC_YEARS_REG, bin2bcd(tm->tm_year % 100));
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omap_rtc_writeb(priv, OMAP_RTC_MONTHS_REG, bin2bcd(tm->tm_mon));
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omap_rtc_writeb(priv, OMAP_RTC_WEEKS_REG, bin2bcd(tm->tm_wday));
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omap_rtc_writeb(priv, OMAP_RTC_DAYS_REG, bin2bcd(tm->tm_mday));
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omap_rtc_writeb(priv, OMAP_RTC_HOURS_REG, bin2bcd(tm->tm_hour));
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omap_rtc_writeb(priv, OMAP_RTC_MINUTES_REG, bin2bcd(tm->tm_min));
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omap_rtc_writeb(priv, OMAP_RTC_SECONDS_REG, bin2bcd(tm->tm_sec));
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omap_rtc_lock(priv);
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dev_dbg(dev, "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
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tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour,
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tm->tm_min, tm->tm_sec);
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return 0;
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}
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static int omap_rtc_get(struct udevice *dev, struct rtc_time *tm)
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{
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struct omap_rtc_priv *priv = dev_get_priv(dev);
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unsigned long sec, min, hour, mday, wday, mon_cent, year;
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int ret;
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ret = omap_rtc_wait_not_busy(priv);
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if (ret)
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return ret;
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sec = omap_rtc_readb(priv, OMAP_RTC_SECONDS_REG);
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min = omap_rtc_readb(priv, OMAP_RTC_MINUTES_REG);
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hour = omap_rtc_readb(priv, OMAP_RTC_HOURS_REG);
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mday = omap_rtc_readb(priv, OMAP_RTC_DAYS_REG);
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wday = omap_rtc_readb(priv, OMAP_RTC_WEEKS_REG);
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mon_cent = omap_rtc_readb(priv, OMAP_RTC_MONTHS_REG);
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year = omap_rtc_readb(priv, OMAP_RTC_YEARS_REG);
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dev_dbg(dev,
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"Get RTC year: %02lx mon/cent: %02lx mday: %02lx wday: %02lx "
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"hr: %02lx min: %02lx sec: %02lx\n",
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year, mon_cent, mday, wday,
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hour, min, sec);
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tm->tm_sec = bcd2bin(sec & 0x7F);
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tm->tm_min = bcd2bin(min & 0x7F);
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tm->tm_hour = bcd2bin(hour & 0x3F);
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tm->tm_mday = bcd2bin(mday & 0x3F);
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tm->tm_mon = bcd2bin(mon_cent & 0x1F);
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tm->tm_year = bcd2bin(year) + 2000;
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tm->tm_wday = bcd2bin(wday & 0x07);
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tm->tm_yday = 0;
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tm->tm_isdst = 0;
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dev_dbg(dev, "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
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tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour,
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tm->tm_min, tm->tm_sec);
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return 0;
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}
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static int omap_rtc_scratch_read(struct udevice *dev, uint offset,
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u8 *buffer, uint len)
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{
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struct omap_rtc_priv *priv = dev_get_priv(dev);
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u32 *val = (u32 *)buffer;
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unsigned int reg;
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int i;
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if (len & 3)
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return -EFAULT;
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for (i = 0; i < len / 4; i++) {
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reg = OMAP_RTC_SCRATCH0_REG + offset + (i * 4);
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if (reg >= OMAP_RTC_KICK0_REG)
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return -EFAULT;
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val[i] = omap_rtc_readl(priv, reg);
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}
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return 0;
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}
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static int omap_rtc_scratch_write(struct udevice *dev, uint offset,
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const u8 *buffer, uint len)
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{
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struct omap_rtc_priv *priv = dev_get_priv(dev);
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u32 *val = (u32 *)buffer;
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unsigned int reg;
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int i;
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if (len & 3)
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return -EFAULT;
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omap_rtc_unlock(priv);
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for (i = 0; i < len / 4; i++) {
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reg = OMAP_RTC_SCRATCH0_REG + offset + (i * 4);
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if (reg >= OMAP_RTC_KICK0_REG)
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return -EFAULT;
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omap_rtc_writel(priv, reg, val[i]);
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}
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omap_rtc_lock(priv);
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return 0;
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}
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static int omap_rtc_remove(struct udevice *dev)
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{
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struct omap_rtc_priv *priv = dev_get_priv(dev);
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u8 reg;
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if (priv->clk.dev)
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clk_disable(&priv->clk);
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omap_rtc_unlock(priv);
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/* leave rtc running, but disable irqs */
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omap_rtc_writeb(priv, OMAP_RTC_INTERRUPTS_REG, 0);
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if (priv->has_ext_clk) {
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reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG);
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reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
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omap_rtc_writeb(priv, OMAP_RTC_OSC_REG, reg);
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}
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omap_rtc_lock(priv);
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return 0;
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}
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static int omap_rtc_probe(struct udevice *dev)
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{
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struct omap_rtc_priv *priv = dev_get_priv(dev);
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struct rtc_time tm;
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u8 reg, mask, new_ctrl;
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priv->dev = dev;
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priv->type = (struct omap_rtc_device_type *)dev_get_driver_data(dev);
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priv->max_reg = OMAP_RTC_PMIC_REG;
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if (!clk_get_by_name(dev, "ext-clk", &priv->clk))
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priv->has_ext_clk = true;
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else
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clk_get_by_name(dev, "int-clk", &priv->clk);
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if (priv->clk.dev)
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clk_enable(&priv->clk);
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else
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dev_warn(dev, "missing clock\n");
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omap_rtc_unlock(priv);
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/*
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* disable interrupts
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*
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* NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
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*/
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omap_rtc_writel(priv, OMAP_RTC_INTERRUPTS_REG, 0);
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if (priv->type->has_32kclk_en) {
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reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG);
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omap_rtc_writeb(priv, OMAP_RTC_OSC_REG,
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reg | OMAP_RTC_OSC_32KCLK_EN);
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}
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/* clear old status */
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reg = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG);
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mask = OMAP_RTC_STATUS_ALARM;
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if (priv->type->has_pmic_mode)
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mask |= OMAP_RTC_STATUS_ALARM2;
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if (priv->type->has_power_up_reset) {
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mask |= OMAP_RTC_STATUS_POWER_UP;
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if (reg & OMAP_RTC_STATUS_POWER_UP)
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dev_info(dev, "RTC power up reset detected\n");
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}
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if (reg & mask)
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omap_rtc_writeb(priv, OMAP_RTC_STATUS_REG, reg & mask);
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/* On boards with split power, RTC_ON_NOFF won't reset the RTC */
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reg = omap_rtc_readb(priv, OMAP_RTC_CTRL_REG);
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if (reg & OMAP_RTC_CTRL_STOP)
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dev_info(dev, "already running\n");
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/* force to 24 hour mode */
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new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
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new_ctrl |= OMAP_RTC_CTRL_STOP;
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/*
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* BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
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*
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* - Device wake-up capability setting should come through chip
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* init logic. OMAP1 boards should initialize the "wakeup capable"
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* flag in the platform device if the board is wired right for
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* being woken up by RTC alarm. For OMAP-L138, this capability
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* is built into the SoC by the "Deep Sleep" capability.
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*
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* - Boards wired so RTC_ON_nOFF is used as the reset signal,
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* rather than nPWRON_RESET, should forcibly enable split
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* power mode. (Some chip errata report that RTC_CTRL_SPLIT
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* is write-only, and always reads as zero...)
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*/
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if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
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dev_info(dev, "split power mode\n");
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if (reg != new_ctrl)
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omap_rtc_writeb(priv, OMAP_RTC_CTRL_REG, new_ctrl);
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/*
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* If we have the external clock then switch to it so we can keep
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* ticking across suspend.
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*/
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if (priv->has_ext_clk) {
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reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG);
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reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE;
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reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC;
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omap_rtc_writeb(priv, OMAP_RTC_OSC_REG, reg);
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}
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omap_rtc_lock(priv);
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if (omap_rtc_get(dev, &tm)) {
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dev_err(dev, "failed to get datetime\n");
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} else if (tm.tm_year == 2000 && tm.tm_mon == 1 && tm.tm_mday == 1 &&
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tm.tm_wday == 0) {
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tm.tm_wday = 6;
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omap_rtc_set(dev, &tm);
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}
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return 0;
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}
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static int omap_rtc_of_to_plat(struct udevice *dev)
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{
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struct omap_rtc_priv *priv = dev_get_priv(dev);
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priv->base = dev_read_addr(dev);
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if (priv->base == FDT_ADDR_T_NONE) {
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dev_err(dev, "invalid address\n");
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return -EINVAL;
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}
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dev_dbg(dev, "base=%pa\n", &priv->base);
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return 0;
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}
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static const struct rtc_ops omap_rtc_ops = {
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.get = omap_rtc_get,
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.set = omap_rtc_set,
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.reset = omap_rtc_reset,
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.read = omap_rtc_scratch_read,
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.write = omap_rtc_scratch_write,
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};
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static const struct omap_rtc_device_type omap_rtc_am3352_type = {
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.has_32kclk_en = true,
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.has_irqwakeen = true,
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.has_pmic_mode = true,
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};
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static const struct omap_rtc_device_type omap_rtc_da830_type = {
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.has_32kclk_en = false,
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.has_irqwakeen = false,
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.has_pmic_mode = false,
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};
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static const struct udevice_id omap_rtc_ids[] = {
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{.compatible = "ti,am3352-rtc", .data = (ulong)&omap_rtc_am3352_type},
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{.compatible = "ti,da830-rtc", .data = (ulong)&omap_rtc_da830_type }
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};
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U_BOOT_DRIVER(omap_rtc) = {
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.name = "omap_rtc",
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.id = UCLASS_RTC,
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.of_match = omap_rtc_ids,
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.ops = &omap_rtc_ops,
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.of_to_plat = omap_rtc_of_to_plat,
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.probe = omap_rtc_probe,
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.remove = omap_rtc_remove,
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.priv_auto = sizeof(struct omap_rtc_priv),
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};
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