mirror of
https://github.com/AsahiLinux/u-boot
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8b85dfc675
At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
746 lines
18 KiB
C
746 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek PCIe host controller driver.
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*
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* Copyright (c) 2017-2019 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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* Honghui Zhang <honghui.zhang@mediatek.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <generic-phy.h>
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#include <log.h>
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#include <malloc.h>
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#include <pci.h>
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#include <reset.h>
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#include <asm/io.h>
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#include <dm/devres.h>
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#include <linux/bitops.h>
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#include <linux/iopoll.h>
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#include <linux/list.h>
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#include "pci_internal.h"
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/* PCIe shared registers */
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#define PCIE_SYS_CFG 0x00
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#define PCIE_INT_ENABLE 0x0c
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#define PCIE_CFG_ADDR 0x20
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#define PCIE_CFG_DATA 0x24
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/* PCIe per port registers */
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#define PCIE_BAR0_SETUP 0x10
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#define PCIE_CLASS 0x34
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#define PCIE_LINK_STATUS 0x50
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#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
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#define PCIE_PORT_PERST(x) BIT(1 + (x))
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#define PCIE_PORT_LINKUP BIT(0)
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#define PCIE_BAR_MAP_MAX GENMASK(31, 16)
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#define PCIE_BAR_ENABLE BIT(0)
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#define PCIE_REVISION_ID BIT(0)
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#define PCIE_CLASS_CODE (0x60400 << 8)
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#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
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((((regn) >> 8) & GENMASK(3, 0)) << 24))
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#define PCIE_CONF_ADDR(regn, bdf) \
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(PCIE_CONF_REG(regn) | (bdf))
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/* MediaTek specific configuration registers */
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#define PCIE_FTS_NUM 0x70c
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#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
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#define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
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#define PCIE_FC_CREDIT 0x73c
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#define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
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#define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
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/* PCIe V2 share registers */
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#define PCIE_SYS_CFG_V2 0x0
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#define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8)
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#define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
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/* PCIe V2 per-port registers */
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#define PCIE_CONF_VEND_ID 0x100
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#define PCIE_CONF_DEVICE_ID 0x102
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#define PCIE_CONF_CLASS_ID 0x106
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#define PCIE_AHB_TRANS_BASE0_L 0x438
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#define PCIE_AHB_TRANS_BASE0_H 0x43c
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#define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
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#define PCIE_AXI_WINDOW0 0x448
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#define WIN_ENABLE BIT(7)
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/*
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* Define PCIe to AHB window size as 2^33 to support max 8GB address space
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* translate, support least 4GB DRAM size access from EP DMA(physical DRAM
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* start from 0x40000000).
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*/
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#define PCIE2AHB_SIZE 0x21
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/* PCIe V2 configuration transaction header */
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#define PCIE_CFG_HEADER0 0x460
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#define PCIE_CFG_HEADER1 0x464
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#define PCIE_CFG_HEADER2 0x468
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#define PCIE_CFG_WDATA 0x470
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#define PCIE_APP_TLP_REQ 0x488
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#define PCIE_CFG_RDATA 0x48c
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#define APP_CFG_REQ BIT(0)
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#define APP_CPL_STATUS GENMASK(7, 5)
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#define CFG_WRRD_TYPE_0 4
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#define CFG_WR_FMT 2
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#define CFG_RD_FMT 0
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#define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
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#define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
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#define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
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#define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))
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#define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))
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#define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))
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#define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))
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#define CFG_HEADER_DW0(type, fmt) \
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(CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
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#define CFG_HEADER_DW1(where, size) \
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(GENMASK(((size) - 1), 0) << ((where) & 0x3))
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#define CFG_HEADER_DW2(regn, fun, dev, bus) \
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(CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
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CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
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#define PCIE_RST_CTRL 0x510
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#define PCIE_PHY_RSTB BIT(0)
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#define PCIE_PIPE_SRSTB BIT(1)
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#define PCIE_MAC_SRSTB BIT(2)
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#define PCIE_CRSTB BIT(3)
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#define PCIE_PERSTB BIT(8)
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#define PCIE_LINKDOWN_RST_EN GENMASK(15, 13)
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#define PCIE_LINK_STATUS_V2 0x804
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#define PCIE_PORT_LINKUP_V2 BIT(11)
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#define PCI_VENDOR_ID_MEDIATEK 0x14c3
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enum MTK_PCIE_GEN {PCIE_V1, PCIE_V2, PCIE_V3};
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struct mtk_pcie_port {
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void __iomem *base;
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struct list_head list;
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struct mtk_pcie *pcie;
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struct reset_ctl reset;
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struct clk sys_ck;
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struct clk ahb_ck;
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struct clk axi_ck;
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struct clk aux_ck;
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struct clk obff_ck;
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struct clk pipe_ck;
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struct phy phy;
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u32 slot;
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};
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struct mtk_pcie {
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void __iomem *base;
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void *priv;
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struct clk free_ck;
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struct list_head ports;
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};
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static int mtk_pcie_config_address(const struct udevice *udev, pci_dev_t bdf,
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uint offset, void **paddress)
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{
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struct mtk_pcie *pcie = dev_get_priv(udev);
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writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR);
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*paddress = pcie->base + PCIE_CFG_DATA + (offset & 3);
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return 0;
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}
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static int mtk_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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return pci_generic_mmap_read_config(bus, mtk_pcie_config_address,
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bdf, offset, valuep, size);
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}
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static int mtk_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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return pci_generic_mmap_write_config(bus, mtk_pcie_config_address,
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bdf, offset, value, size);
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}
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static const struct dm_pci_ops mtk_pcie_ops = {
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.read_config = mtk_pcie_read_config,
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.write_config = mtk_pcie_write_config,
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};
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static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
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{
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u32 val;
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int err;
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err = readl_poll_timeout(port->base + PCIE_APP_TLP_REQ, val,
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!(val & APP_CFG_REQ), 100 * 1000);
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if (err)
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return -1;
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if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
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return -1;
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return 0;
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}
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static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, pci_dev_t devfn,
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int where, int size, ulong *val)
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{
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u32 tmp;
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writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
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port->base + PCIE_CFG_HEADER0);
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writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
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writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_DEV(devfn), bus),
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port->base + PCIE_CFG_HEADER2);
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/* Trigger h/w to transmit Cfgrd TLP */
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tmp = readl(port->base + PCIE_APP_TLP_REQ);
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tmp |= APP_CFG_REQ;
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writel(tmp, port->base + PCIE_APP_TLP_REQ);
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/* Check completion status */
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if (mtk_pcie_check_cfg_cpld(port))
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return -1;
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/* Read cpld payload of Cfgrd */
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*val = readl(port->base + PCIE_CFG_RDATA);
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if (size == 1)
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*val = (*val >> (8 * (where & 3))) & 0xff;
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else if (size == 2)
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*val = (*val >> (8 * (where & 3))) & 0xffff;
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return 0;
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}
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static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, pci_dev_t devfn,
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int where, int size, u32 val)
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{
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/* Write PCIe configuration transaction header for Cfgwr */
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writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
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port->base + PCIE_CFG_HEADER0);
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writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
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writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_DEV(devfn), bus),
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port->base + PCIE_CFG_HEADER2);
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/* Write Cfgwr data */
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val = val << 8 * (where & 3);
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writel(val, port->base + PCIE_CFG_WDATA);
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/* Trigger h/w to transmit Cfgwr TLP */
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val = readl(port->base + PCIE_APP_TLP_REQ);
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val |= APP_CFG_REQ;
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writel(val, port->base + PCIE_APP_TLP_REQ);
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/* Check completion status */
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return mtk_pcie_check_cfg_cpld(port);
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}
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static struct mtk_pcie_port *mtk_pcie_find_port(const struct udevice *bus,
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pci_dev_t bdf)
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{
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struct mtk_pcie *pcie = dev_get_priv(bus);
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struct mtk_pcie_port *port;
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struct udevice *dev;
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struct pci_child_plat *pplat = NULL;
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int ret = 0;
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if (PCI_BUS(bdf) != 0) {
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ret = pci_get_bus(PCI_BUS(bdf), &dev);
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if (ret) {
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debug("No such device,ret = %d\n", ret);
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return NULL;
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}
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while (dev_seq(dev->parent) != 0)
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dev = dev->parent;
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pplat = dev_get_parent_plat(dev);
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}
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list_for_each_entry(port, &pcie->ports, list) {
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if ((PCI_BUS(bdf) == 0) && (PCI_DEV(bdf) == port->slot))
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return port;
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if (PCI_BUS(bdf) != 0 && PCI_DEV(bdf) == 0 &&
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PCI_DEV(pplat->devfn) == port->slot)
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return port;
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}
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return NULL;
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}
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static int mtk_pcie_config_read(const struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct mtk_pcie_port *port;
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int ret;
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port = mtk_pcie_find_port(bus, bdf);
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if (!port) {
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*valuep = pci_get_ff(size);
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return 0;
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}
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ret = mtk_pcie_hw_rd_cfg(port, PCI_BUS(bdf), bdf, offset, (1 << size), valuep);
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if (ret)
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*valuep = pci_get_ff(size);
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return ret;
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}
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static int mtk_pcie_config_write(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct mtk_pcie_port *port;
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port = mtk_pcie_find_port(bus, bdf);
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if (!port)
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return 0;
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/* Do not modify RC bar 0/1. */
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if (PCI_BUS(bdf) == 0 && (offset == 0x10 || offset == 0x14))
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return 0;
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return mtk_pcie_hw_wr_cfg(port, PCI_BUS(bdf), bdf, offset, (1 << size), value);
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}
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static const struct dm_pci_ops mtk_pcie_ops_v2 = {
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.read_config = mtk_pcie_config_read,
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.write_config = mtk_pcie_config_write,
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};
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static void mtk_pcie_port_free(struct mtk_pcie_port *port)
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{
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list_del(&port->list);
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free(port);
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}
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static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
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{
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struct mtk_pcie *pcie = port->pcie;
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u32 slot = PCI_DEV(port->slot << 11);
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u32 val;
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int err;
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/* assert port PERST_N */
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setbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
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/* de-assert port PERST_N */
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clrbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
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/* 100ms timeout value should be enough for Gen1/2 training */
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err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
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!!(val & PCIE_PORT_LINKUP), 100000);
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if (err)
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return -ETIMEDOUT;
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/* disable interrupt */
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clrbits_le32(pcie->base + PCIE_INT_ENABLE,
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PCIE_PORT_INT_EN(port->slot));
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/* map to all DDR region. We need to set it before cfg operation. */
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writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
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port->base + PCIE_BAR0_SETUP);
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/* configure class code and revision ID */
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writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
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/* configure FC credit */
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writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot),
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pcie->base + PCIE_CFG_ADDR);
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clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FC_CREDIT_MASK,
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PCIE_FC_CREDIT_VAL(0x806c));
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/* configure RC FTS number to 250 when it leaves L0s */
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writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR);
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clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FTS_NUM_MASK,
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PCIE_FTS_NUM_L0(0x50));
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return 0;
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}
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static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
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{
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struct mtk_pcie *pcie = port->pcie;
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struct udevice *dev = pcie->priv;
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struct pci_region *pci_mem;
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u32 val;
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int err;
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/* MT7622/MT7629 platforms need to enable LTSSM and ASPM from PCIe subsys */
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if (pcie->base) {
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val = readl(pcie->base + PCIE_SYS_CFG_V2);
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val |= PCIE_CSR_LTSSM_EN(port->slot) |
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PCIE_CSR_ASPM_L1_EN(port->slot);
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writel(val, pcie->base + PCIE_SYS_CFG_V2);
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}
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/* Assert all reset signals */
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writel(0, port->base + PCIE_RST_CTRL);
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/*
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* Enable PCIe link down reset, if link status changed from link up to
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* link down, this will reset MAC control registers and configuration
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* space.
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*/
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writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
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udelay(500);
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/* De-assert PHY, PE, PIPE, MAC and configuration reset */
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val = readl(port->base + PCIE_RST_CTRL);
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val |= PCIE_PHY_RSTB | PCIE_PIPE_SRSTB | PCIE_MAC_SRSTB | PCIE_CRSTB;
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writel(val, port->base + PCIE_RST_CTRL);
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mdelay(100);
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val |= PCIE_PERSTB;
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writel(val, port->base + PCIE_RST_CTRL);
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/* Set up vendor ID and class code */
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val = PCI_VENDOR_ID_MEDIATEK;
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writew(val, port->base + PCIE_CONF_VEND_ID);
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val = PCI_CLASS_BRIDGE_PCI;
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writew(val, port->base + PCIE_CONF_CLASS_ID);
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/* 100ms timeout value should be enough for Gen1/2 training */
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err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
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!!(val & PCIE_PORT_LINKUP_V2),
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100 * 1000);
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if (err)
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return -ETIMEDOUT;
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pci_get_regions(dev, NULL, &pci_mem, NULL);
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/* Set AHB to PCIe translation windows */
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val = lower_32_bits(pci_mem->bus_start) |
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AHB2PCIE_SIZE(fls(pci_mem->size) - 1);
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writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
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val = upper_32_bits(pci_mem->bus_start);
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writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
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/* Set PCIe to AXI translation memory space.*/
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val = PCIE2AHB_SIZE | WIN_ENABLE;
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writel(val, port->base + PCIE_AXI_WINDOW0);
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return 0;
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}
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static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
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{
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int err;
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err = clk_enable(&port->sys_ck);
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if (err)
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goto err_sys_clk;
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err = reset_assert(&port->reset);
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if (err)
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|
goto err_reset;
|
|
|
|
err = reset_deassert(&port->reset);
|
|
if (err)
|
|
goto err_reset;
|
|
|
|
err = generic_phy_init(&port->phy);
|
|
if (err)
|
|
goto err_phy_init;
|
|
|
|
err = generic_phy_power_on(&port->phy);
|
|
if (err)
|
|
goto err_phy_on;
|
|
|
|
if (!mtk_pcie_startup_port(port))
|
|
return;
|
|
|
|
pr_err("Port%d link down\n", port->slot);
|
|
|
|
generic_phy_power_off(&port->phy);
|
|
err_phy_on:
|
|
generic_phy_exit(&port->phy);
|
|
err_phy_init:
|
|
err_reset:
|
|
clk_disable(&port->sys_ck);
|
|
err_sys_clk:
|
|
mtk_pcie_port_free(port);
|
|
}
|
|
|
|
static void mtk_pcie_enable_port_v2(struct mtk_pcie_port *port)
|
|
{
|
|
int err = 0;
|
|
|
|
err = clk_enable(&port->sys_ck);
|
|
if (err) {
|
|
debug("clk_enable(sys_ck) failed: %d\n", err);
|
|
goto exit;
|
|
}
|
|
|
|
err = clk_enable(&port->ahb_ck);
|
|
if (err) {
|
|
debug("clk_enable(ahb_ck) failed: %d\n", err);
|
|
goto exit;
|
|
}
|
|
|
|
err = clk_enable(&port->aux_ck);
|
|
if (err) {
|
|
debug("clk_enable(aux_ck) failed: %d\n", err);
|
|
goto exit;
|
|
}
|
|
|
|
err = clk_enable(&port->axi_ck);
|
|
if (err) {
|
|
debug("clk_enable(axi_ck) failed: %d\n", err);
|
|
goto exit;
|
|
}
|
|
|
|
err = clk_enable(&port->obff_ck);
|
|
if (err) {
|
|
debug("clk_enable(obff_ck) failed: %d\n", err);
|
|
goto exit;
|
|
}
|
|
|
|
err = clk_enable(&port->pipe_ck);
|
|
if (err) {
|
|
debug("clk_enable(pipe_ck) failed: %d\n", err);
|
|
goto exit;
|
|
}
|
|
|
|
err = mtk_pcie_startup_port_v2(port);
|
|
if (!err)
|
|
return;
|
|
|
|
pr_err("Port%d link down\n", port->slot);
|
|
exit:
|
|
mtk_pcie_port_free(port);
|
|
}
|
|
|
|
static int mtk_pcie_parse_port(struct udevice *dev, u32 slot)
|
|
{
|
|
struct mtk_pcie *pcie = dev_get_priv(dev);
|
|
struct mtk_pcie_port *port;
|
|
char name[10];
|
|
int err;
|
|
|
|
port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
|
|
if (!port)
|
|
return -ENOMEM;
|
|
|
|
snprintf(name, sizeof(name), "port%d", slot);
|
|
port->base = dev_remap_addr_name(dev, name);
|
|
if (!port->base)
|
|
return -ENOENT;
|
|
|
|
snprintf(name, sizeof(name), "sys_ck%d", slot);
|
|
err = clk_get_by_name(dev, name, &port->sys_ck);
|
|
if (err)
|
|
return err;
|
|
|
|
err = reset_get_by_index(dev, slot, &port->reset);
|
|
if (err)
|
|
return err;
|
|
|
|
err = generic_phy_get_by_index(dev, slot, &port->phy);
|
|
if (err)
|
|
return err;
|
|
|
|
port->slot = slot;
|
|
port->pcie = pcie;
|
|
|
|
INIT_LIST_HEAD(&port->list);
|
|
list_add_tail(&port->list, &pcie->ports);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_pcie_parse_port_v2(struct udevice *dev, u32 slot)
|
|
{
|
|
struct mtk_pcie *pcie = dev_get_priv(dev);
|
|
struct mtk_pcie_port *port;
|
|
char name[10];
|
|
int err;
|
|
|
|
port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
|
|
if (!port)
|
|
return -ENOMEM;
|
|
|
|
snprintf(name, sizeof(name), "port%d", slot);
|
|
port->base = dev_remap_addr_name(dev, name);
|
|
if (!port->base) {
|
|
debug("failed to map port%d base\n", slot);
|
|
return -ENOENT;
|
|
}
|
|
|
|
snprintf(name, sizeof(name), "sys_ck%d", slot);
|
|
err = clk_get_by_name(dev, name, &port->sys_ck);
|
|
if (err) {
|
|
debug("clk_get_by_name(sys_ck) failed: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
snprintf(name, sizeof(name), "ahb_ck%d", slot);
|
|
err = clk_get_by_name(dev, name, &port->ahb_ck);
|
|
if (err) {
|
|
debug("clk_get_by_name(ahb_ck) failed: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
snprintf(name, sizeof(name), "aux_ck%d", slot);
|
|
err = clk_get_by_name(dev, name, &port->aux_ck);
|
|
if (err) {
|
|
debug("clk_get_by_name(aux_ck) failed: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
snprintf(name, sizeof(name), "axi_ck%d", slot);
|
|
err = clk_get_by_name(dev, name, &port->axi_ck);
|
|
if (err) {
|
|
debug("clk_get_by_name(axi_ck) failed: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
snprintf(name, sizeof(name), "obff_ck%d", slot);
|
|
err = clk_get_by_name(dev, name, &port->obff_ck);
|
|
if (err) {
|
|
debug("clk_get_by_name(obff_ck) failed: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
snprintf(name, sizeof(name), "pipe_ck%d", slot);
|
|
err = clk_get_by_name(dev, name, &port->pipe_ck);
|
|
if (err) {
|
|
debug("clk_get_by_name(pipe_ck) failed: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
port->slot = slot;
|
|
port->pcie = pcie;
|
|
|
|
INIT_LIST_HEAD(&port->list);
|
|
list_add_tail(&port->list, &pcie->ports);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_pcie_probe(struct udevice *dev)
|
|
{
|
|
struct mtk_pcie *pcie = dev_get_priv(dev);
|
|
struct mtk_pcie_port *port, *tmp;
|
|
ofnode subnode;
|
|
int err;
|
|
|
|
INIT_LIST_HEAD(&pcie->ports);
|
|
|
|
pcie->base = dev_remap_addr_name(dev, "subsys");
|
|
if (!pcie->base)
|
|
return -ENOENT;
|
|
|
|
err = clk_get_by_name(dev, "free_ck", &pcie->free_ck);
|
|
if (err)
|
|
return err;
|
|
|
|
/* enable top level clock */
|
|
err = clk_enable(&pcie->free_ck);
|
|
if (err)
|
|
return err;
|
|
|
|
dev_for_each_subnode(subnode, dev) {
|
|
struct fdt_pci_addr addr;
|
|
u32 slot = 0;
|
|
|
|
if (!ofnode_is_available(subnode))
|
|
continue;
|
|
|
|
err = ofnode_read_pci_addr(subnode, 0, "reg", &addr);
|
|
if (err)
|
|
return err;
|
|
|
|
slot = PCI_DEV(addr.phys_hi);
|
|
|
|
err = mtk_pcie_parse_port(dev, slot);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
/* enable each port, and then check link status */
|
|
list_for_each_entry_safe(port, tmp, &pcie->ports, list)
|
|
mtk_pcie_enable_port(port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_pcie_probe_v2(struct udevice *dev)
|
|
{
|
|
struct mtk_pcie *pcie = dev_get_priv(dev);
|
|
struct mtk_pcie_port *port, *tmp;
|
|
struct fdt_pci_addr addr;
|
|
ofnode subnode;
|
|
unsigned int slot;
|
|
int err;
|
|
|
|
INIT_LIST_HEAD(&pcie->ports);
|
|
|
|
pcie->base = dev_remap_addr_name(dev, "subsys");
|
|
if (!pcie->base)
|
|
return -ENOENT;
|
|
|
|
pcie->priv = dev;
|
|
|
|
dev_for_each_subnode(subnode, dev) {
|
|
if (!ofnode_is_available(subnode))
|
|
continue;
|
|
|
|
err = ofnode_read_pci_addr(subnode, 0, "reg", &addr);
|
|
if (err)
|
|
return err;
|
|
|
|
slot = PCI_DEV(addr.phys_hi);
|
|
err = mtk_pcie_parse_port_v2(dev, slot);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
/* enable each port, and then check link status */
|
|
list_for_each_entry_safe(port, tmp, &pcie->ports, list)
|
|
mtk_pcie_enable_port_v2(port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id mtk_pcie_ids[] = {
|
|
{ .compatible = "mediatek,mt7623-pcie", PCIE_V1},
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(pcie_mediatek_v1) = {
|
|
.name = "pcie_mediatek_v1",
|
|
.id = UCLASS_PCI,
|
|
.of_match = mtk_pcie_ids,
|
|
.ops = &mtk_pcie_ops,
|
|
.probe = mtk_pcie_probe,
|
|
.priv_auto = sizeof(struct mtk_pcie),
|
|
};
|
|
|
|
static const struct udevice_id mtk_pcie_ids_v2[] = {
|
|
{ .compatible = "mediatek,mt7622-pcie", PCIE_V2},
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(pcie_mediatek_v2) = {
|
|
.name = "pcie_mediatek_v2",
|
|
.id = UCLASS_PCI,
|
|
.of_match = mtk_pcie_ids_v2,
|
|
.ops = &mtk_pcie_ops_v2,
|
|
.probe = mtk_pcie_probe_v2,
|
|
.priv_auto = sizeof(struct mtk_pcie),
|
|
};
|