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https://github.com/AsahiLinux/u-boot
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be38416034
In the current code, it doesn't reset the cursors of LUT entry and StreamID at the beginning of the fixup, so it can result in LUT entry setup and msi-map mismatch and LUT entries and StreamID leaking when reload and fixup the DTB. This patch move the initialization of LUT entry and StreamID cursors to the beginning of the fixup to resolve the issues. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
248 lines
6.3 KiB
C
248 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Copyright 2018-2021 NXP
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*
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* PCIe Gen4 driver for NXP Layerscape SoCs
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* Author: Hou Zhiqiang <Minder.Hou@gmail.com>
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*
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <pci.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/io.h>
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#include <errno.h>
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#ifdef CONFIG_OF_BOARD_SETUP
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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#ifdef CONFIG_ARM
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#include <asm/arch/clock.h>
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#endif
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#include "pcie_layerscape_gen4.h"
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#include "pcie_layerscape_fixup_common.h"
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#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
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/*
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* Return next available LUT index.
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*/
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static int ls_pcie_g4_next_lut_index(struct ls_pcie_g4 *pcie)
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{
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if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
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return pcie->next_lut_index++;
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return -ENOSPC; /* LUT is full */
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}
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/*
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* Program a single LUT entry
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*/
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static void ls_pcie_g4_lut_set_mapping(struct ls_pcie_g4 *pcie, int index,
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u32 devid, u32 streamid)
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{
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/* leave mask as all zeroes, want to match all bits */
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lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
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lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
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}
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/*
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* An msi-map is a property to be added to the pci controller
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* node. It is a table, where each entry consists of 4 fields
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* e.g.:
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*
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* msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
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* [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
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*/
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static void fdt_pcie_set_msi_map_entry_ls_gen4(void *blob,
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struct ls_pcie_g4 *pcie,
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u32 devid, u32 streamid)
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{
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u32 *prop;
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u32 phandle;
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int nodeoff;
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#ifdef CONFIG_FSL_PCIE_COMPAT
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nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
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pcie->ccsr_res.start);
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#else
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#error "No CONFIG_FSL_PCIE_COMPAT defined"
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#endif
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if (nodeoff < 0) {
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debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
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return;
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}
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/* get phandle to MSI controller */
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prop = (u32 *)fdt_getprop(blob, nodeoff, "msi-parent", 0);
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if (!prop) {
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debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
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__func__, pcie->idx);
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return;
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}
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phandle = fdt32_to_cpu(*prop);
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/* set one msi-map row */
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fdt_appendprop_u32(blob, nodeoff, "msi-map", devid);
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fdt_appendprop_u32(blob, nodeoff, "msi-map", phandle);
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fdt_appendprop_u32(blob, nodeoff, "msi-map", streamid);
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fdt_appendprop_u32(blob, nodeoff, "msi-map", 1);
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}
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/*
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* An iommu-map is a property to be added to the pci controller
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* node. It is a table, where each entry consists of 4 fields
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* e.g.:
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*
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* iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
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* [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
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*/
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static void fdt_pcie_set_iommu_map_entry_ls_gen4(void *blob,
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struct ls_pcie_g4 *pcie,
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u32 devid, u32 streamid)
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{
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u32 *prop;
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u32 iommu_map[4];
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int nodeoff;
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int lenp;
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#ifdef CONFIG_FSL_PCIE_COMPAT
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nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
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pcie->ccsr_res.start);
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#else
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#error "No CONFIG_FSL_PCIE_COMPAT defined"
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#endif
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if (nodeoff < 0) {
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debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
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return;
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}
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/* get phandle to iommu controller */
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prop = fdt_getprop_w(blob, nodeoff, "iommu-map", &lenp);
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if (!prop) {
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debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
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__func__, pcie->idx);
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return;
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}
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/* set iommu-map row */
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iommu_map[0] = cpu_to_fdt32(devid);
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iommu_map[1] = *++prop;
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iommu_map[2] = cpu_to_fdt32(streamid);
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iommu_map[3] = cpu_to_fdt32(1);
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if (devid == 0)
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fdt_setprop_inplace(blob, nodeoff, "iommu-map", iommu_map, 16);
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else
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fdt_appendprop(blob, nodeoff, "iommu-map", iommu_map, 16);
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}
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static void fdt_fixup_pcie_ls_gen4(void *blob)
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{
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struct udevice *dev, *bus;
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struct ls_pcie_g4 *pcie;
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int streamid;
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int index;
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pci_dev_t bdf;
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/* Scan all known buses */
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for (pci_find_first_device(&dev); dev; pci_find_next_device(&dev)) {
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for (bus = dev; device_is_on_pci_bus(bus);)
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bus = bus->parent;
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pcie = dev_get_priv(bus);
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streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
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if (streamid < 0) {
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debug("ERROR: no stream ids free\n");
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continue;
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} else {
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pcie->stream_id_cur++;
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}
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index = ls_pcie_g4_next_lut_index(pcie);
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if (index < 0) {
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debug("ERROR: no LUT indexes free\n");
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continue;
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}
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/* the DT fixup must be relative to the hose first_busno */
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bdf = dm_pci_get_bdf(dev) - PCI_BDF(dev_seq(bus), 0, 0);
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/* map PCI b.d.f to streamID in LUT */
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ls_pcie_g4_lut_set_mapping(pcie, index, bdf >> 8, streamid);
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/* update msi-map in device tree */
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fdt_pcie_set_msi_map_entry_ls_gen4(blob, pcie, bdf >> 8,
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streamid);
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/* update iommu-map in device tree */
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fdt_pcie_set_iommu_map_entry_ls_gen4(blob, pcie, bdf >> 8,
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streamid);
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}
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}
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#endif
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static void ft_pcie_ep_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
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{
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int off;
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off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
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pcie->ccsr_res.start);
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if (off < 0) {
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debug("%s: ERROR: failed to find pcie compatiable\n",
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__func__);
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return;
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}
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if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
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fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
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else
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fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
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}
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static void ft_pcie_rc_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
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{
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int off;
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#ifdef CONFIG_FSL_PCIE_COMPAT
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off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
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pcie->ccsr_res.start);
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#else
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#error "No CONFIG_FSL_PCIE_COMPAT defined"
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#endif
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if (off < 0) {
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debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
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return;
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}
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if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
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fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
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else
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fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
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}
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static void ft_pcie_layerscape_gen4_setup(void *blob, struct ls_pcie_g4 *pcie)
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{
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ft_pcie_rc_layerscape_gen4_fix(blob, pcie);
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ft_pcie_ep_layerscape_gen4_fix(blob, pcie);
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pcie->stream_id_cur = 0;
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pcie->next_lut_index = 0;
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}
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/* Fixup Kernel DT for PCIe */
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void ft_pci_setup_ls_gen4(void *blob, struct bd_info *bd)
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{
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struct ls_pcie_g4 *pcie;
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list_for_each_entry(pcie, &ls_pcie_g4_list, list)
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ft_pcie_layerscape_gen4_setup(blob, pcie);
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#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
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fdt_fixup_pcie_ls_gen4(blob);
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#endif
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}
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#else /* !CONFIG_OF_BOARD_SETUP */
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void ft_pci_setup_ls_gen4(void *blob, struct bd_info *bd)
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{
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}
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#endif
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