mirror of
https://github.com/AsahiLinux/u-boot
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be38416034
In the current code, it doesn't reset the cursors of LUT entry and StreamID at the beginning of the fixup, so it can result in LUT entry setup and msi-map mismatch and LUT entries and StreamID leaking when reload and fixup the DTB. This patch move the initialization of LUT entry and StreamID cursors to the beginning of the fixup to resolve the issues. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
583 lines
15 KiB
C
583 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Copyright 2018-2021 NXP
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*
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* PCIe Gen4 driver for NXP Layerscape SoCs
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* Author: Hou Zhiqiang <Minder.Hou@gmail.com>
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*/
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#include <common.h>
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#include <log.h>
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#include <asm/arch/fsl_serdes.h>
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#include <pci.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <malloc.h>
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#include <dm.h>
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#include <linux/sizes.h>
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#include "pcie_layerscape_gen4.h"
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DECLARE_GLOBAL_DATA_PTR;
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LIST_HEAD(ls_pcie_g4_list);
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static u64 bar_size[4] = {
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PCIE_BAR0_SIZE,
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PCIE_BAR1_SIZE,
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PCIE_BAR2_SIZE,
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PCIE_BAR4_SIZE
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};
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static int ls_pcie_g4_ltssm(struct ls_pcie_g4 *pcie)
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{
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u32 state;
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state = pf_ctrl_readl(pcie, PCIE_LTSSM_STA) & LTSSM_STATE_MASK;
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return state;
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}
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static int ls_pcie_g4_link_up(struct ls_pcie_g4 *pcie)
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{
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int ltssm;
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ltssm = ls_pcie_g4_ltssm(pcie);
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if (ltssm != LTSSM_PCIE_L0)
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return 0;
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return 1;
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}
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static void ls_pcie_g4_ep_enable_cfg(struct ls_pcie_g4 *pcie)
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{
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ccsr_writel(pcie, GPEX_CFG_READY, PCIE_CONFIG_READY);
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}
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static void ls_pcie_g4_cfg_set_target(struct ls_pcie_g4 *pcie, u32 target)
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{
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ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_L(0), target);
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ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_H(0), 0);
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}
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static int ls_pcie_g4_outbound_win_set(struct ls_pcie_g4 *pcie, int idx,
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int type, u64 phys, u64 bus_addr,
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pci_size_t size)
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{
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u32 val;
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u32 size_h, size_l;
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if (idx >= PAB_WINS_NUM)
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return -EINVAL;
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size_h = upper_32_bits(~(size - 1));
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size_l = lower_32_bits(~(size - 1));
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val = ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(idx));
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val &= ~((AXI_AMAP_CTRL_TYPE_MASK << AXI_AMAP_CTRL_TYPE_SHIFT) |
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(AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT) |
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AXI_AMAP_CTRL_EN);
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val |= ((type & AXI_AMAP_CTRL_TYPE_MASK) << AXI_AMAP_CTRL_TYPE_SHIFT) |
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((size_l >> AXI_AMAP_CTRL_SIZE_SHIFT) <<
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AXI_AMAP_CTRL_SIZE_SHIFT) | AXI_AMAP_CTRL_EN;
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ccsr_writel(pcie, PAB_AXI_AMAP_CTRL(idx), val);
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ccsr_writel(pcie, PAB_AXI_AMAP_AXI_WIN(idx), lower_32_bits(phys));
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ccsr_writel(pcie, PAB_EXT_AXI_AMAP_AXI_WIN(idx), upper_32_bits(phys));
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ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_L(idx), lower_32_bits(bus_addr));
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ccsr_writel(pcie, PAB_AXI_AMAP_PEX_WIN_H(idx), upper_32_bits(bus_addr));
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ccsr_writel(pcie, PAB_EXT_AXI_AMAP_SIZE(idx), size_h);
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return 0;
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}
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static int ls_pcie_g4_rc_inbound_win_set(struct ls_pcie_g4 *pcie, int idx,
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int type, u64 phys, u64 bus_addr,
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pci_size_t size)
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{
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u32 val;
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pci_size_t win_size = ~(size - 1);
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val = ccsr_readl(pcie, PAB_PEX_AMAP_CTRL(idx));
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val &= ~(PEX_AMAP_CTRL_TYPE_MASK << PEX_AMAP_CTRL_TYPE_SHIFT);
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val &= ~(PEX_AMAP_CTRL_EN_MASK << PEX_AMAP_CTRL_EN_SHIFT);
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val = (val | (type << PEX_AMAP_CTRL_TYPE_SHIFT));
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val = (val | (1 << PEX_AMAP_CTRL_EN_SHIFT));
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ccsr_writel(pcie, PAB_PEX_AMAP_CTRL(idx),
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val | lower_32_bits(win_size));
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ccsr_writel(pcie, PAB_EXT_PEX_AMAP_SIZE(idx), upper_32_bits(win_size));
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ccsr_writel(pcie, PAB_PEX_AMAP_AXI_WIN(idx), lower_32_bits(phys));
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ccsr_writel(pcie, PAB_EXT_PEX_AMAP_AXI_WIN(idx), upper_32_bits(phys));
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ccsr_writel(pcie, PAB_PEX_AMAP_PEX_WIN_L(idx), lower_32_bits(bus_addr));
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ccsr_writel(pcie, PAB_PEX_AMAP_PEX_WIN_H(idx), upper_32_bits(bus_addr));
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return 0;
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}
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static void ls_pcie_g4_dump_wins(struct ls_pcie_g4 *pcie, int wins)
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{
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int i;
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for (i = 0; i < wins; i++) {
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debug("APIO Win%d:\n", i);
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debug("\tLOWER PHYS: 0x%08x\n",
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ccsr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(i)));
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debug("\tUPPER PHYS: 0x%08x\n",
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ccsr_readl(pcie, PAB_EXT_AXI_AMAP_AXI_WIN(i)));
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debug("\tLOWER BUS: 0x%08x\n",
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ccsr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_L(i)));
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debug("\tUPPER BUS: 0x%08x\n",
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ccsr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(i)));
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debug("\tSIZE: 0x%08x\n",
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ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(i)) &
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(AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT));
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debug("\tEXT_SIZE: 0x%08x\n",
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ccsr_readl(pcie, PAB_EXT_AXI_AMAP_SIZE(i)));
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debug("\tPARAM: 0x%08x\n",
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ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(i)));
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debug("\tCTRL: 0x%08x\n",
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ccsr_readl(pcie, PAB_AXI_AMAP_CTRL(i)));
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}
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}
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static void ls_pcie_g4_setup_wins(struct ls_pcie_g4 *pcie)
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{
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struct pci_region *io, *mem, *pref;
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int idx = 1;
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/* INBOUND WIN */
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ls_pcie_g4_rc_inbound_win_set(pcie, 0, IB_TYPE_MEM_F, 0, 0, SIZE_1T);
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/* OUTBOUND WIN 0: CFG */
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ls_pcie_g4_outbound_win_set(pcie, 0, PAB_AXI_TYPE_CFG,
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pcie->cfg_res.start, 0,
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fdt_resource_size(&pcie->cfg_res));
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pci_get_regions(pcie->bus, &io, &mem, &pref);
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if (io)
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/* OUTBOUND WIN: IO */
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ls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_IO,
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io->phys_start, io->bus_start,
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io->size);
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if (mem)
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/* OUTBOUND WIN: MEM */
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ls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_MEM,
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mem->phys_start, mem->bus_start,
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mem->size);
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if (pref)
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/* OUTBOUND WIN: perf MEM */
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ls_pcie_g4_outbound_win_set(pcie, idx++, PAB_AXI_TYPE_MEM,
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pref->phys_start, pref->bus_start,
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pref->size);
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ls_pcie_g4_dump_wins(pcie, idx);
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}
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/* Return 0 if the address is valid, -errno if not valid */
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static int ls_pcie_g4_addr_valid(struct ls_pcie_g4 *pcie, pci_dev_t bdf)
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{
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struct udevice *bus = pcie->bus;
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if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
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return -ENODEV;
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if (!pcie->enabled)
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return -ENXIO;
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if (PCI_BUS(bdf) < dev_seq(bus))
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return -EINVAL;
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if ((PCI_BUS(bdf) > dev_seq(bus)) && (!ls_pcie_g4_link_up(pcie)))
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return -EINVAL;
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if (PCI_BUS(bdf) <= (dev_seq(bus) + 1) && (PCI_DEV(bdf) > 0))
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return -EINVAL;
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return 0;
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}
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void *ls_pcie_g4_conf_address(struct ls_pcie_g4 *pcie, pci_dev_t bdf,
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int offset)
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{
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struct udevice *bus = pcie->bus;
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u32 target;
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if (PCI_BUS(bdf) == dev_seq(bus)) {
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if (offset < INDIRECT_ADDR_BNDRY) {
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ccsr_set_page(pcie, 0);
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return pcie->ccsr + offset;
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}
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ccsr_set_page(pcie, OFFSET_TO_PAGE_IDX(offset));
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return pcie->ccsr + OFFSET_TO_PAGE_ADDR(offset);
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}
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target = PAB_TARGET_BUS(PCI_BUS(bdf) - dev_seq(bus)) |
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PAB_TARGET_DEV(PCI_DEV(bdf)) |
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PAB_TARGET_FUNC(PCI_FUNC(bdf));
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ls_pcie_g4_cfg_set_target(pcie, target);
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return pcie->cfg + offset;
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}
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static int ls_pcie_g4_read_config(const struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct ls_pcie_g4 *pcie = dev_get_priv(bus);
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void *address;
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int ret = 0;
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if (ls_pcie_g4_addr_valid(pcie, bdf)) {
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*valuep = pci_get_ff(size);
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return 0;
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}
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address = ls_pcie_g4_conf_address(pcie, bdf, offset);
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switch (size) {
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case PCI_SIZE_8:
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*valuep = readb(address);
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break;
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case PCI_SIZE_16:
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*valuep = readw(address);
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break;
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case PCI_SIZE_32:
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*valuep = readl(address);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int ls_pcie_g4_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct ls_pcie_g4 *pcie = dev_get_priv(bus);
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void *address;
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if (ls_pcie_g4_addr_valid(pcie, bdf))
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return 0;
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address = ls_pcie_g4_conf_address(pcie, bdf, offset);
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switch (size) {
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case PCI_SIZE_8:
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writeb(value, address);
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return 0;
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case PCI_SIZE_16:
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writew(value, address);
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return 0;
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case PCI_SIZE_32:
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writel(value, address);
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return 0;
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default:
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return -EINVAL;
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}
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}
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static void ls_pcie_g4_setup_ctrl(struct ls_pcie_g4 *pcie)
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{
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u32 val;
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/* Fix class code */
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val = ccsr_readl(pcie, GPEX_CLASSCODE);
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val &= ~(GPEX_CLASSCODE_MASK << GPEX_CLASSCODE_SHIFT);
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val |= PCI_CLASS_BRIDGE_PCI << GPEX_CLASSCODE_SHIFT;
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ccsr_writel(pcie, GPEX_CLASSCODE, val);
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/* Enable APIO and Memory/IO/CFG Wins */
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val = ccsr_readl(pcie, PAB_AXI_PIO_CTRL(0));
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val |= APIO_EN | MEM_WIN_EN | IO_WIN_EN | CFG_WIN_EN;
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ccsr_writel(pcie, PAB_AXI_PIO_CTRL(0), val);
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ls_pcie_g4_setup_wins(pcie);
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}
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static void ls_pcie_g4_ep_inbound_win_set(struct ls_pcie_g4 *pcie, int pf,
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int bar, u64 phys)
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{
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u32 val;
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/* PF BAR1 is for MSI-X and only need to enable */
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if (bar == 1) {
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ccsr_writel(pcie, PAB_PEX_BAR_AMAP(pf, bar), BAR_AMAP_EN);
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return;
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}
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val = upper_32_bits(phys);
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ccsr_writel(pcie, PAB_EXT_PEX_BAR_AMAP(pf, bar), val);
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val = lower_32_bits(phys) | BAR_AMAP_EN;
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ccsr_writel(pcie, PAB_PEX_BAR_AMAP(pf, bar), val);
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}
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static void ls_pcie_g4_ep_setup_wins(struct ls_pcie_g4 *pcie, int pf)
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{
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u64 phys;
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int bar;
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u32 val;
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if ((!pcie->sriov_support && pf > LS_G4_PF0) || pf > LS_G4_PF1)
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return;
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phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf;
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for (bar = 0; bar < PF_BAR_NUM; bar++) {
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ls_pcie_g4_ep_inbound_win_set(pcie, pf, bar, phys);
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phys += PCIE_BAR_SIZE;
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}
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/* OUTBOUND: map MEM */
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ls_pcie_g4_outbound_win_set(pcie, pf, PAB_AXI_TYPE_MEM,
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pcie->cfg_res.start +
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CONFIG_SYS_PCI_MEMORY_SIZE * pf, 0x0,
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CONFIG_SYS_PCI_MEMORY_SIZE);
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val = ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf));
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val &= ~FUNC_NUM_PCIE_MASK;
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val |= pf;
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ccsr_writel(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf), val);
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}
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static void ls_pcie_g4_ep_enable_bar(struct ls_pcie_g4 *pcie, int pf,
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int bar, bool vf_bar, bool enable)
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{
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u32 val;
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u32 bar_pos = BAR_POS(bar, pf, vf_bar);
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val = ccsr_readl(pcie, GPEX_BAR_ENABLE);
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if (enable)
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val |= 1 << bar_pos;
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else
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val &= ~(1 << bar_pos);
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ccsr_writel(pcie, GPEX_BAR_ENABLE, val);
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}
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static void ls_pcie_g4_ep_set_bar_size(struct ls_pcie_g4 *pcie, int pf,
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int bar, bool vf_bar, u64 size)
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{
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u32 bar_pos = BAR_POS(bar, pf, vf_bar);
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u32 mask_l = lower_32_bits(~(size - 1));
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u32 mask_h = upper_32_bits(~(size - 1));
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ccsr_writel(pcie, GPEX_BAR_SELECT, bar_pos);
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ccsr_writel(pcie, GPEX_BAR_SIZE_LDW, mask_l);
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ccsr_writel(pcie, GPEX_BAR_SIZE_UDW, mask_h);
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}
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static void ls_pcie_g4_ep_setup_bar(struct ls_pcie_g4 *pcie, int pf,
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int bar, bool vf_bar, u64 size)
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{
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bool en = size ? true : false;
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ls_pcie_g4_ep_enable_bar(pcie, pf, bar, vf_bar, en);
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ls_pcie_g4_ep_set_bar_size(pcie, pf, bar, vf_bar, size);
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}
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static void ls_pcie_g4_ep_setup_bars(struct ls_pcie_g4 *pcie, int pf)
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{
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int bar;
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/* Setup PF BARs */
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for (bar = 0; bar < PF_BAR_NUM; bar++)
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ls_pcie_g4_ep_setup_bar(pcie, pf, bar, false, bar_size[bar]);
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if (!pcie->sriov_support)
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return;
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/* Setup VF BARs */
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for (bar = 0; bar < VF_BAR_NUM; bar++)
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ls_pcie_g4_ep_setup_bar(pcie, pf, bar, true, bar_size[bar]);
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}
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static void ls_pcie_g4_set_sriov(struct ls_pcie_g4 *pcie, int pf)
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{
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unsigned int val;
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val = ccsr_readl(pcie, GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf));
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val &= ~(TTL_VF_MASK << TTL_VF_SHIFT);
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val |= PCIE_VF_NUM << TTL_VF_SHIFT;
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val &= ~(INI_VF_MASK << INI_VF_SHIFT);
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val |= PCIE_VF_NUM << INI_VF_SHIFT;
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ccsr_writel(pcie, GPEX_SRIOV_INIT_VFS_TOTAL_VF(pf), val);
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val = ccsr_readl(pcie, PCIE_SRIOV_VF_OFFSET_STRIDE);
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val += PCIE_VF_NUM * pf - pf;
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ccsr_writel(pcie, GPEX_SRIOV_VF_OFFSET_STRIDE(pf), val);
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}
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static void ls_pcie_g4_setup_ep(struct ls_pcie_g4 *pcie)
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{
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u32 pf, sriov;
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u32 val;
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int i;
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/* Enable APIO and Memory Win */
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val = ccsr_readl(pcie, PAB_AXI_PIO_CTRL(0));
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val |= APIO_EN | MEM_WIN_EN;
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ccsr_writel(pcie, PAB_AXI_PIO_CTRL(0), val);
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sriov = ccsr_readl(pcie, PCIE_SRIOV_CAPABILITY);
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if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)
|
|
pcie->sriov_support = 1;
|
|
|
|
pf = pcie->sriov_support ? PCIE_PF_NUM : 1;
|
|
|
|
for (i = 0; i < pf; i++) {
|
|
ls_pcie_g4_ep_setup_bars(pcie, i);
|
|
ls_pcie_g4_ep_setup_wins(pcie, i);
|
|
if (pcie->sriov_support)
|
|
ls_pcie_g4_set_sriov(pcie, i);
|
|
}
|
|
|
|
ls_pcie_g4_ep_enable_cfg(pcie);
|
|
ls_pcie_g4_dump_wins(pcie, pf);
|
|
}
|
|
|
|
static int ls_pcie_g4_probe(struct udevice *dev)
|
|
{
|
|
struct ls_pcie_g4 *pcie = dev_get_priv(dev);
|
|
const void *fdt = gd->fdt_blob;
|
|
int node = dev_of_offset(dev);
|
|
u32 link_ctrl_sta;
|
|
u32 val;
|
|
int ret;
|
|
fdt_size_t cfg_size;
|
|
|
|
pcie->bus = dev;
|
|
|
|
ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
|
|
"ccsr", &pcie->ccsr_res);
|
|
if (ret) {
|
|
printf("ls-pcie-g4: resource \"ccsr\" not found\n");
|
|
return ret;
|
|
}
|
|
|
|
pcie->idx = (pcie->ccsr_res.start - PCIE_SYS_BASE_ADDR) /
|
|
PCIE_CCSR_SIZE;
|
|
|
|
list_add(&pcie->list, &ls_pcie_g4_list);
|
|
|
|
pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
|
|
if (!pcie->enabled) {
|
|
printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
|
|
dev->name);
|
|
return 0;
|
|
}
|
|
|
|
pcie->ccsr = map_physmem(pcie->ccsr_res.start,
|
|
fdt_resource_size(&pcie->ccsr_res),
|
|
MAP_NOCACHE);
|
|
|
|
ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
|
|
"config", &pcie->cfg_res);
|
|
if (ret) {
|
|
printf("%s: resource \"config\" not found\n", dev->name);
|
|
return ret;
|
|
}
|
|
|
|
cfg_size = fdt_resource_size(&pcie->cfg_res);
|
|
if (cfg_size < SZ_4K) {
|
|
printf("PCIe%d: %s Invalid size(0x%llx) for resource \"config\",expected minimum 0x%x\n",
|
|
PCIE_SRDS_PRTCL(pcie->idx), dev->name, cfg_size, SZ_4K);
|
|
return 0;
|
|
}
|
|
|
|
pcie->cfg = map_physmem(pcie->cfg_res.start,
|
|
fdt_resource_size(&pcie->cfg_res),
|
|
MAP_NOCACHE);
|
|
|
|
ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
|
|
"lut", &pcie->lut_res);
|
|
if (ret) {
|
|
printf("ls-pcie-g4: resource \"lut\" not found\n");
|
|
return ret;
|
|
}
|
|
|
|
pcie->lut = map_physmem(pcie->lut_res.start,
|
|
fdt_resource_size(&pcie->lut_res),
|
|
MAP_NOCACHE);
|
|
|
|
ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
|
|
"pf_ctrl", &pcie->pf_ctrl_res);
|
|
if (ret) {
|
|
printf("ls-pcie-g4: resource \"pf_ctrl\" not found\n");
|
|
return ret;
|
|
}
|
|
|
|
pcie->pf_ctrl = map_physmem(pcie->pf_ctrl_res.start,
|
|
fdt_resource_size(&pcie->pf_ctrl_res),
|
|
MAP_NOCACHE);
|
|
|
|
pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
|
|
|
|
debug("%s ccsr:%lx, cfg:0x%lx, big-endian:%d\n",
|
|
dev->name, (unsigned long)pcie->ccsr, (unsigned long)pcie->cfg,
|
|
pcie->big_endian);
|
|
|
|
pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f;
|
|
|
|
if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
|
|
printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
|
|
"Endpoint");
|
|
ls_pcie_g4_setup_ep(pcie);
|
|
} else {
|
|
printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
|
|
"Root Complex");
|
|
ls_pcie_g4_setup_ctrl(pcie);
|
|
}
|
|
|
|
/* Enable Amba & PEX PIO */
|
|
val = ccsr_readl(pcie, PAB_CTRL);
|
|
val |= PAB_CTRL_APIO_EN | PAB_CTRL_PPIO_EN;
|
|
ccsr_writel(pcie, PAB_CTRL, val);
|
|
|
|
val = ccsr_readl(pcie, PAB_PEX_PIO_CTRL(0));
|
|
val |= PPIO_EN;
|
|
ccsr_writel(pcie, PAB_PEX_PIO_CTRL(0), val);
|
|
|
|
if (!ls_pcie_g4_link_up(pcie)) {
|
|
/* Let the user know there's no PCIe link */
|
|
printf(": no link\n");
|
|
return 0;
|
|
}
|
|
|
|
/* Print the negotiated PCIe link width */
|
|
link_ctrl_sta = ccsr_readl(pcie, PCIE_LINK_CTRL_STA);
|
|
printf(": x%d gen%d\n",
|
|
(link_ctrl_sta >> PCIE_LINK_WIDTH_SHIFT & PCIE_LINK_WIDTH_MASK),
|
|
(link_ctrl_sta >> PCIE_LINK_SPEED_SHIFT) & PCIE_LINK_SPEED_MASK);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_pci_ops ls_pcie_g4_ops = {
|
|
.read_config = ls_pcie_g4_read_config,
|
|
.write_config = ls_pcie_g4_write_config,
|
|
};
|
|
|
|
static const struct udevice_id ls_pcie_g4_ids[] = {
|
|
{ .compatible = "fsl,lx2160a-pcie" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(pcie_layerscape_gen4) = {
|
|
.name = "pcie_layerscape_gen4",
|
|
.id = UCLASS_PCI,
|
|
.of_match = ls_pcie_g4_ids,
|
|
.ops = &ls_pcie_g4_ops,
|
|
.probe = ls_pcie_g4_probe,
|
|
.priv_auto = sizeof(struct ls_pcie_g4),
|
|
};
|