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https://github.com/AsahiLinux/u-boot
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1a03182967
Migrate the dw_ti driver to use the common DW PCIe helpers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
361 lines
8.3 KiB
C
361 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Texas Instruments, Inc
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <pci.h>
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#include <generic-phy.h>
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#include <power-domain.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm-generic/gpio.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include "pcie_dw_common.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define PCIE_VENDORID_MASK GENMASK(15, 0)
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#define PCIE_DEVICEID_SHIFT 16
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#define PCIE_LINK_CAPABILITY 0x7c
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#define PCIE_LINK_CTL_2 0xa0
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#define TARGET_LINK_SPEED_MASK 0xf
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#define LINK_SPEED_GEN_1 0x1
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#define LINK_SPEED_GEN_2 0x2
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#define LINK_SPEED_GEN_3 0x3
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#define PCIE_MISC_CONTROL_1_OFF 0x8bc
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#define PCIE_DBI_RO_WR_EN BIT(0)
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#define PLR_OFFSET 0x700
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#define PCIE_PORT_DEBUG0 (PLR_OFFSET + 0x28)
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#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
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#define PORT_LOGIC_LTSSM_STATE_L0 0x11
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#define PCIE_LINK_UP_TIMEOUT_MS 100
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/* Offsets from App base */
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#define PCIE_CMD_STATUS 0x04
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#define LTSSM_EN_VAL BIT(0)
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#define AM654_PCIE_DEV_TYPE_MASK 0x3
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#define EP 0x0
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#define LEG_EP 0x1
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#define RC 0x2
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/**
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* struct pcie_dw_ti - TI DW PCIe controller state
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*
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* @pci: The common PCIe DW structure
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* @app_base: The base address of application register space
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*/
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struct pcie_dw_ti {
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/* Must be first member of the struct */
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struct pcie_dw dw;
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void *app_base;
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};
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enum dw_pcie_device_mode {
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DW_PCIE_UNKNOWN_TYPE,
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DW_PCIE_EP_TYPE,
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DW_PCIE_LEG_EP_TYPE,
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DW_PCIE_RC_TYPE,
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};
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/**
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* pcie_dw_configure() - Configure link capabilities and speed
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*
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* @regs_base: A pointer to the PCIe controller registers
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* @cap_speed: The capabilities and speed to configure
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*
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* Configure the link capabilities and speed in the PCIe root complex.
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*/
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static void pcie_dw_configure(struct pcie_dw_ti *pci, u32 cap_speed)
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{
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u32 val;
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dw_pcie_dbi_write_enable(&pci->dw, true);
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val = readl(pci->dw.dbi_base + PCIE_LINK_CAPABILITY);
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val &= ~TARGET_LINK_SPEED_MASK;
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val |= cap_speed;
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writel(val, pci->dw.dbi_base + PCIE_LINK_CAPABILITY);
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val = readl(pci->dw.dbi_base + PCIE_LINK_CTL_2);
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val &= ~TARGET_LINK_SPEED_MASK;
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val |= cap_speed;
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writel(val, pci->dw.dbi_base + PCIE_LINK_CTL_2);
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dw_pcie_dbi_write_enable(&pci->dw, false);
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}
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/**
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* is_link_up() - Return the link state
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*
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* @regs_base: A pointer to the PCIe DBICS registers
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*
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* Return: 1 (true) for active line and 0 (false) for no link
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*/
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static int is_link_up(struct pcie_dw_ti *pci)
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{
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u32 val;
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val = readl(pci->dw.dbi_base + PCIE_PORT_DEBUG0);
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val &= PORT_LOGIC_LTSSM_STATE_MASK;
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return (val == PORT_LOGIC_LTSSM_STATE_L0);
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}
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/**
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* wait_link_up() - Wait for the link to come up
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*
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* @regs_base: A pointer to the PCIe controller registers
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*
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* Return: 1 (true) for active line and 0 (false) for no link (timeout)
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*/
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static int wait_link_up(struct pcie_dw_ti *pci)
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{
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unsigned long timeout;
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timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
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while (!is_link_up(pci)) {
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if (get_timer(0) > timeout)
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return 0;
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};
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return 1;
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}
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static int pcie_dw_ti_pcie_link_up(struct pcie_dw_ti *pci, u32 cap_speed)
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{
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u32 val;
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if (is_link_up(pci)) {
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printf("PCI Link already up before configuration!\n");
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return 1;
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}
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/* DW pre link configurations */
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pcie_dw_configure(pci, cap_speed);
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/* Initiate link training */
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val = readl(pci->app_base + PCIE_CMD_STATUS);
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val |= LTSSM_EN_VAL;
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writel(val, pci->app_base + PCIE_CMD_STATUS);
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/* Check that link was established */
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if (!wait_link_up(pci))
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return 0;
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/*
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* Link can be established in Gen 1. still need to wait
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* till MAC nagaotiation is completed
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*/
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udelay(100);
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return 1;
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}
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static int pcie_am654_set_mode(struct pcie_dw_ti *pci,
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enum dw_pcie_device_mode mode)
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{
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struct regmap *syscon;
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u32 val;
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u32 mask;
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int ret;
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syscon = syscon_regmap_lookup_by_phandle(pci->dw.dev,
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"ti,syscon-pcie-mode");
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if (IS_ERR(syscon))
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return 0;
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mask = AM654_PCIE_DEV_TYPE_MASK;
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switch (mode) {
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case DW_PCIE_RC_TYPE:
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val = RC;
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break;
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case DW_PCIE_EP_TYPE:
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val = EP;
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break;
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default:
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dev_err(pci->dw.dev, "INVALID device type %d\n", mode);
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return -EINVAL;
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}
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ret = regmap_update_bits(syscon, 0, mask, val);
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if (ret) {
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dev_err(pci->dw.dev, "failed to set pcie mode\n");
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return ret;
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}
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return 0;
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}
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static int pcie_dw_init_id(struct pcie_dw_ti *pci)
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{
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struct regmap *devctrl_regs;
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unsigned int id;
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int ret;
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devctrl_regs = syscon_regmap_lookup_by_phandle(pci->dw.dev,
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"ti,syscon-pcie-id");
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if (IS_ERR(devctrl_regs))
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return PTR_ERR(devctrl_regs);
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ret = regmap_read(devctrl_regs, 0, &id);
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if (ret)
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return ret;
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dw_pcie_dbi_write_enable(&pci->dw, true);
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writew(id & PCIE_VENDORID_MASK, pci->dw.dbi_base + PCI_VENDOR_ID);
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writew(id >> PCIE_DEVICEID_SHIFT, pci->dw.dbi_base + PCI_DEVICE_ID);
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dw_pcie_dbi_write_enable(&pci->dw, false);
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return 0;
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}
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/**
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* pcie_dw_ti_probe() - Probe the PCIe bus for active link
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*
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* @dev: A pointer to the device being operated on
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*
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* Probe for an active link on the PCIe bus and configure the controller
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* to enable this port.
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*
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* Return: 0 on success, else -ENODEV
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*/
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static int pcie_dw_ti_probe(struct udevice *dev)
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{
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struct pcie_dw_ti *pci = dev_get_priv(dev);
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struct udevice *ctlr = pci_get_controller(dev);
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struct pci_controller *hose = dev_get_uclass_priv(ctlr);
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struct power_domain pci_pwrdmn;
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struct phy phy0, phy1;
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int ret;
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ret = power_domain_get_by_index(dev, &pci_pwrdmn, 0);
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if (ret) {
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dev_err(dev, "failed to get power domain\n");
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return ret;
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}
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ret = power_domain_on(&pci_pwrdmn);
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if (ret) {
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dev_err(dev, "Power domain on failed\n");
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return ret;
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}
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ret = generic_phy_get_by_name(dev, "pcie-phy0", &phy0);
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if (ret) {
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dev_err(dev, "Unable to get phy0");
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return ret;
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}
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generic_phy_reset(&phy0);
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generic_phy_init(&phy0);
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generic_phy_power_on(&phy0);
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ret = generic_phy_get_by_name(dev, "pcie-phy1", &phy1);
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if (ret) {
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dev_err(dev, "Unable to get phy1");
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return ret;
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}
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generic_phy_reset(&phy1);
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generic_phy_init(&phy1);
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generic_phy_power_on(&phy1);
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pci->dw.first_busno = dev_seq(dev);
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pci->dw.dev = dev;
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pcie_dw_setup_host(&pci->dw);
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pcie_dw_init_id(pci);
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if (device_is_compatible(dev, "ti,am654-pcie-rc"))
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pcie_am654_set_mode(pci, DW_PCIE_RC_TYPE);
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if (!pcie_dw_ti_pcie_link_up(pci, LINK_SPEED_GEN_2)) {
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printf("PCIE-%d: Link down\n", dev_seq(dev));
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return -ENODEV;
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}
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printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev_seq(dev),
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pcie_dw_get_link_speed(&pci->dw),
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pcie_dw_get_link_width(&pci->dw),
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hose->first_busno);
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pcie_dw_prog_outbound_atu_unroll(&pci->dw, PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_MEM,
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pci->dw.mem.phys_start,
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pci->dw.mem.bus_start, pci->dw.mem.size);
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return 0;
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}
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/**
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* pcie_dw_ti_of_to_plat() - Translate from DT to device state
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*
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* @dev: A pointer to the device being operated on
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*
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* Translate relevant data from the device tree pertaining to device @dev into
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* state that the driver will later make use of. This state is stored in the
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* device's private data structure.
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*
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* Return: 0 on success, else -EINVAL
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*/
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static int pcie_dw_ti_of_to_plat(struct udevice *dev)
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{
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struct pcie_dw_ti *pcie = dev_get_priv(dev);
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/* Get the controller base address */
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pcie->dw.dbi_base = (void *)dev_read_addr_name(dev, "dbics");
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if ((fdt_addr_t)pcie->dw.dbi_base == FDT_ADDR_T_NONE)
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return -EINVAL;
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/* Get the config space base address and size */
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pcie->dw.cfg_base = (void *)dev_read_addr_size_name(dev, "config",
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&pcie->dw.cfg_size);
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if ((fdt_addr_t)pcie->dw.cfg_base == FDT_ADDR_T_NONE)
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return -EINVAL;
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/* Get the iATU base address and size */
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pcie->dw.atu_base = (void *)dev_read_addr_name(dev, "atu");
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if ((fdt_addr_t)pcie->dw.atu_base == FDT_ADDR_T_NONE)
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return -EINVAL;
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/* Get the app base address and size */
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pcie->app_base = (void *)dev_read_addr_name(dev, "app");
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if ((fdt_addr_t)pcie->app_base == FDT_ADDR_T_NONE)
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return -EINVAL;
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return 0;
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}
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static const struct dm_pci_ops pcie_dw_ti_ops = {
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.read_config = pcie_dw_read_config,
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.write_config = pcie_dw_write_config,
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};
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static const struct udevice_id pcie_dw_ti_ids[] = {
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{ .compatible = "ti,am654-pcie-rc" },
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{ }
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};
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U_BOOT_DRIVER(pcie_dw_ti) = {
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.name = "pcie_dw_ti",
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.id = UCLASS_PCI,
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.of_match = pcie_dw_ti_ids,
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.ops = &pcie_dw_ti_ops,
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.of_to_plat = pcie_dw_ti_of_to_plat,
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.probe = pcie_dw_ti_probe,
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.priv_auto = sizeof(struct pcie_dw_ti),
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};
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