mirror of
https://github.com/AsahiLinux/u-boot
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88647f078d
Replace msleep occurences by udelay. drivers/pci/pcie_dw_rockchip.c:254:3: warning: implicit declaration of function 'msleep' [-Wimplicit-function-declaration] Cc: Patrick Wildt <patrick@blueri.se> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
462 lines
11 KiB
C
462 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Rockchip DesignWare based PCIe host controller driver
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*
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* Copyright (c) 2021 Rockchip, Inc.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <generic-phy.h>
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#include <pci.h>
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#include <power-domain.h>
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#include <reset.h>
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#include <syscon.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm-generic/gpio.h>
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#include <dm/device_compat.h>
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#include <linux/iopoll.h>
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#include <linux/delay.h>
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#include <power/regulator.h>
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#include "pcie_dw_common.h"
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DECLARE_GLOBAL_DATA_PTR;
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/**
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* struct rk_pcie - RK DW PCIe controller state
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*
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* @vpcie3v3: The 3.3v power supply for slot
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* @apb_base: The base address of vendor regs
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* @rst_gpio: The #PERST signal for slot
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*/
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struct rk_pcie {
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/* Must be first member of the struct */
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struct pcie_dw dw;
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struct udevice *vpcie3v3;
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void *apb_base;
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struct phy phy;
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struct clk_bulk clks;
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struct reset_ctl_bulk rsts;
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struct gpio_desc rst_gpio;
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};
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/* Parameters for the waiting for iATU enabled routine */
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#define PCIE_CLIENT_GENERAL_DEBUG 0x104
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#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
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#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
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#define PCIE_CLIENT_LTSSM_STATUS 0x300
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#define SMLH_LINKUP BIT(16)
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#define RDLH_LINKUP BIT(17)
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#define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310
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#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320
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#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324
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#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328
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#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c
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#define PCIE_CLIENT_DBG_FIFO_STATUS 0x350
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#define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000
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#define PCIE_CLIENT_DBF_EN 0xffff0003
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/* Parameters for the waiting for #perst signal */
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#define MACRO_US 1000
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static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
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{
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if ((uintptr_t)addr & (size - 1)) {
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*val = 0;
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return -EOPNOTSUPP;
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}
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if (size == 4) {
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*val = readl(addr);
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} else if (size == 2) {
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*val = readw(addr);
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} else if (size == 1) {
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*val = readb(addr);
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} else {
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*val = 0;
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return -ENODEV;
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}
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return 0;
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}
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static int rk_pcie_write(void __iomem *addr, int size, u32 val)
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{
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if ((uintptr_t)addr & (size - 1))
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return -EOPNOTSUPP;
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if (size == 4)
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writel(val, addr);
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else if (size == 2)
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writew(val, addr);
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else if (size == 1)
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writeb(val, addr);
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else
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return -ENODEV;
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return 0;
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}
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static u32 __rk_pcie_read_apb(struct rk_pcie *rk_pcie, void __iomem *base,
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u32 reg, size_t size)
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{
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int ret;
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u32 val;
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ret = rk_pcie_read(base + reg, size, &val);
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if (ret)
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dev_err(rk_pcie->dw.dev, "Read APB address failed\n");
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return val;
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}
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static void __rk_pcie_write_apb(struct rk_pcie *rk_pcie, void __iomem *base,
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u32 reg, size_t size, u32 val)
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{
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int ret;
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ret = rk_pcie_write(base + reg, size, val);
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if (ret)
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dev_err(rk_pcie->dw.dev, "Write APB address failed\n");
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}
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/**
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* rk_pcie_readl_apb() - Read vendor regs
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*
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* @rk_pcie: Pointer to the PCI controller state
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* @reg: Offset of regs
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*/
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static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg)
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{
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return __rk_pcie_read_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4);
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}
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/**
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* rk_pcie_writel_apb() - Write vendor regs
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*
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* @rk_pcie: Pointer to the PCI controller state
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* @reg: Offset of regs
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* @val: Value to be writen
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*/
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static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg,
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u32 val)
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{
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__rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val);
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}
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/**
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* rk_pcie_configure() - Configure link capabilities and speed
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*
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* @rk_pcie: Pointer to the PCI controller state
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* @cap_speed: The capabilities and speed to configure
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*
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* Configure the link capabilities and speed in the PCIe root complex.
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*/
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static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed)
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{
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dw_pcie_dbi_write_enable(&pci->dw, true);
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clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY,
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TARGET_LINK_SPEED_MASK, cap_speed);
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clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CTL_2,
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TARGET_LINK_SPEED_MASK, cap_speed);
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dw_pcie_dbi_write_enable(&pci->dw, false);
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}
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static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie)
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{
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rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0,
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PCIE_CLIENT_DBG_TRANSITION_DATA);
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rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1,
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PCIE_CLIENT_DBG_TRANSITION_DATA);
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rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0,
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PCIE_CLIENT_DBG_TRANSITION_DATA);
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rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1,
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PCIE_CLIENT_DBG_TRANSITION_DATA);
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rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_MODE_CON,
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PCIE_CLIENT_DBF_EN);
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}
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static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie)
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{
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u32 loop;
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debug("ltssm = 0x%x\n",
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rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
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for (loop = 0; loop < 64; loop++)
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debug("fifo_status = 0x%x\n",
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rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS));
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}
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static inline void rk_pcie_link_status_clear(struct rk_pcie *rk_pcie)
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{
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rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG, 0x0);
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}
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static inline void rk_pcie_disable_ltssm(struct rk_pcie *rk_pcie)
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{
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rk_pcie_writel_apb(rk_pcie, 0x0, 0xc0008);
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}
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static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie)
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{
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rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c);
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}
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static int is_link_up(struct rk_pcie *priv)
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{
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u32 val;
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val = rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS);
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if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000 &&
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(val & GENMASK(5, 0)) == 0x11)
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return 1;
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return 0;
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}
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/**
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* rk_pcie_link_up() - Wait for the link to come up
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*
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* @rk_pcie: Pointer to the PCI controller state
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* @cap_speed: Desired link speed
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*
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* Return: 1 (true) for active line and negetive (false) for no link (timeout)
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*/
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static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed)
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{
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int retries;
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if (is_link_up(priv)) {
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printf("PCI Link already up before configuration!\n");
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return 1;
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}
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/* DW pre link configurations */
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rk_pcie_configure(priv, cap_speed);
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/* Rest the device */
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if (dm_gpio_is_valid(&priv->rst_gpio)) {
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dm_gpio_set_value(&priv->rst_gpio, 0);
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/*
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* Minimal is 100ms from spec but we see
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* some wired devices need much more, such as 600ms.
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* Add a enough delay to cover all cases.
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*/
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udelay(MACRO_US * 1000);
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dm_gpio_set_value(&priv->rst_gpio, 1);
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}
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rk_pcie_disable_ltssm(priv);
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rk_pcie_link_status_clear(priv);
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rk_pcie_enable_debug(priv);
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/* Enable LTSSM */
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rk_pcie_enable_ltssm(priv);
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for (retries = 0; retries < 5; retries++) {
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if (is_link_up(priv)) {
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dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n",
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rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
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rk_pcie_debug_dump(priv);
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return 0;
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}
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dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n",
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rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
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rk_pcie_debug_dump(priv);
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udelay(MACRO_US * 1000);
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}
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dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev));
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/* Link maybe in Gen switch recovery but we need to wait more 1s */
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udelay(MACRO_US * 1000);
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return -EIO;
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}
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static int rockchip_pcie_init_port(struct udevice *dev)
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{
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int ret;
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u32 val;
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struct rk_pcie *priv = dev_get_priv(dev);
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/* Set power and maybe external ref clk input */
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if (priv->vpcie3v3) {
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ret = regulator_set_value(priv->vpcie3v3, 3300000);
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if (ret) {
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dev_err(priv->dw.dev, "failed to enable vpcie3v3 (ret=%d)\n",
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ret);
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return ret;
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}
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}
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udelay(MACRO_US * 1000);
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ret = generic_phy_init(&priv->phy);
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if (ret) {
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dev_err(dev, "failed to init phy (ret=%d)\n", ret);
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return ret;
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}
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ret = generic_phy_power_on(&priv->phy);
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if (ret) {
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dev_err(dev, "failed to power on phy (ret=%d)\n", ret);
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goto err_exit_phy;
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}
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ret = reset_deassert_bulk(&priv->rsts);
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if (ret) {
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dev_err(dev, "failed to deassert resets (ret=%d)\n", ret);
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goto err_power_off_phy;
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}
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ret = clk_enable_bulk(&priv->clks);
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if (ret) {
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dev_err(dev, "failed to enable clks (ret=%d)\n", ret);
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goto err_deassert_bulk;
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}
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/* LTSSM EN ctrl mode */
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val = rk_pcie_readl_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL);
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val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16);
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rk_pcie_writel_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL, val);
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/* Set RC mode */
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rk_pcie_writel_apb(priv, 0x0, 0xf00040);
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pcie_dw_setup_host(&priv->dw);
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ret = rk_pcie_link_up(priv, LINK_SPEED_GEN_3);
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if (ret < 0)
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goto err_link_up;
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return 0;
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err_link_up:
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clk_disable_bulk(&priv->clks);
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err_deassert_bulk:
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reset_assert_bulk(&priv->rsts);
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err_power_off_phy:
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generic_phy_power_off(&priv->phy);
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err_exit_phy:
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generic_phy_exit(&priv->phy);
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return ret;
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}
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static int rockchip_pcie_parse_dt(struct udevice *dev)
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{
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struct rk_pcie *priv = dev_get_priv(dev);
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int ret;
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priv->dw.dbi_base = (void *)dev_read_addr_index(dev, 0);
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if (!priv->dw.dbi_base)
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return -ENODEV;
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dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base);
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priv->apb_base = (void *)dev_read_addr_index(dev, 1);
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if (!priv->apb_base)
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return -ENODEV;
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dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base);
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ret = gpio_request_by_name(dev, "reset-gpios", 0,
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&priv->rst_gpio, GPIOD_IS_OUT);
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if (ret) {
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dev_err(dev, "failed to find reset-gpios property\n");
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return ret;
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}
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ret = reset_get_bulk(dev, &priv->rsts);
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if (ret) {
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dev_err(dev, "Can't get reset: %d\n", ret);
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return ret;
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}
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ret = clk_get_bulk(dev, &priv->clks);
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if (ret) {
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dev_err(dev, "Can't get clock: %d\n", ret);
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return ret;
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}
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ret = device_get_supply_regulator(dev, "vpcie3v3-supply",
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&priv->vpcie3v3);
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if (ret && ret != -ENOENT) {
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dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret);
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return ret;
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}
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ret = generic_phy_get_by_index(dev, 0, &priv->phy);
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if (ret) {
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dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret);
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return ret;
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}
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return 0;
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}
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/**
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* rockchip_pcie_probe() - Probe the PCIe bus for active link
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*
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* @dev: A pointer to the device being operated on
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*
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* Probe for an active link on the PCIe bus and configure the controller
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* to enable this port.
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*
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* Return: 0 on success, else -ENODEV
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*/
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static int rockchip_pcie_probe(struct udevice *dev)
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{
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struct rk_pcie *priv = dev_get_priv(dev);
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struct udevice *ctlr = pci_get_controller(dev);
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struct pci_controller *hose = dev_get_uclass_priv(ctlr);
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int ret = 0;
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priv->dw.first_busno = dev_seq(dev);
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priv->dw.dev = dev;
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ret = rockchip_pcie_parse_dt(dev);
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if (ret)
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return ret;
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ret = rockchip_pcie_init_port(dev);
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if (ret)
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return ret;
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dev_info(dev, "PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n",
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dev_seq(dev), pcie_dw_get_link_speed(&priv->dw),
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pcie_dw_get_link_width(&priv->dw),
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hose->first_busno);
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return pcie_dw_prog_outbound_atu_unroll(&priv->dw,
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PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_MEM,
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priv->dw.mem.phys_start,
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priv->dw.mem.bus_start,
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priv->dw.mem.size);
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}
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static const struct dm_pci_ops rockchip_pcie_ops = {
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.read_config = pcie_dw_read_config,
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.write_config = pcie_dw_write_config,
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};
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static const struct udevice_id rockchip_pcie_ids[] = {
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{ .compatible = "rockchip,rk3568-pcie" },
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{ }
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};
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U_BOOT_DRIVER(rockchip_dw_pcie) = {
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.name = "pcie_dw_rockchip",
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.id = UCLASS_PCI,
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.of_match = rockchip_pcie_ids,
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.ops = &rockchip_pcie_ops,
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.probe = rockchip_pcie_probe,
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.priv_auto = sizeof(struct rk_pcie),
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};
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