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8461ee5115
At present the driver only supports 32-bit bus and cpu address. The controller's outbound registers/fields for extended address are not programmed. Let's program them to support 64-bit bus and cpu address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
162 lines
4.1 KiB
C
162 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2019
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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*/
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#include <common.h>
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#include <asm/bitops.h>
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#include <asm/cpm_85xx.h>
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#include <pci.h>
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#include <dm.h>
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#include <asm/fsl_law.h>
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struct mpc85xx_pci_priv {
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void __iomem *cfg_addr;
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void __iomem *cfg_data;
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};
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static int mpc85xx_pci_dm_read_config(const struct udevice *dev, pci_dev_t bdf,
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uint offset, ulong *value,
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enum pci_size_t size)
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{
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struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
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u32 addr;
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addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
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out_be32(priv->cfg_addr, addr);
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sync();
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*value = pci_conv_32_to_size(in_le32(priv->cfg_data), offset, size);
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return 0;
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}
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static int mpc85xx_pci_dm_write_config(struct udevice *dev, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
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u32 addr;
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addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
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out_be32(priv->cfg_addr, addr);
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sync();
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out_le32(priv->cfg_data, pci_conv_size_to_32(0, value, offset, size));
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return 0;
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}
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#ifdef CONFIG_FSL_LAW
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static int
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mpc85xx_pci_dm_setup_laws(struct pci_region *io, struct pci_region *mem,
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struct pci_region *pre)
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{
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/*
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* Unfortunately we have defines for this addresse,
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* as we have to setup the TLB, and at this stage
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* we have no access to DT ... may we check here
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* if the value in the define is the same ?
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*/
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if (mem)
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set_next_law(mem->phys_start, law_size_bits(mem->size),
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LAW_TRGT_IF_PCI);
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if (io)
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set_next_law(io->phys_start, law_size_bits(io->size),
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LAW_TRGT_IF_PCI);
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if (pre)
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set_next_law(pre->phys_start, law_size_bits(pre->size),
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LAW_TRGT_IF_PCI);
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return 0;
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}
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#endif
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static int mpc85xx_pci_dm_probe(struct udevice *dev)
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{
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struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
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struct pci_region *io;
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struct pci_region *mem;
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struct pci_region *pre;
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int count;
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ccsr_pcix_t *pcix;
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count = pci_get_regions(dev, &io, &mem, &pre);
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if (count != 2) {
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printf("%s: wrong count of regions %d only 2 allowed\n",
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__func__, count);
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return -EINVAL;
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}
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#ifdef CONFIG_FSL_LAW
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mpc85xx_pci_dm_setup_laws(io, mem, pre);
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#endif
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pcix = priv->cfg_addr;
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/* BAR 1: memory */
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out_be32(&pcix->potar1, mem->bus_start >> 12);
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out_be32(&pcix->potear1, (u64)mem->bus_start >> 44);
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out_be32(&pcix->powbar1, mem->phys_start >> 12);
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out_be32(&pcix->powbear1, (u64)mem->phys_start >> 44);
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out_be32(&pcix->powar1, (POWAR_EN | POWAR_MEM_READ |
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POWAR_MEM_WRITE | (__ilog2(mem->size) - 1)));
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/* BAR 1: IO */
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out_be32(&pcix->potar2, io->bus_start >> 12);
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out_be32(&pcix->potear2, (u64)io->bus_start >> 44);
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out_be32(&pcix->powbar2, io->phys_start >> 12);
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out_be32(&pcix->powbear2, (u64)io->phys_start >> 44);
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out_be32(&pcix->powar2, (POWAR_EN | POWAR_IO_READ |
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POWAR_IO_WRITE | (__ilog2(io->size) - 1)));
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out_be32(&pcix->pitar1, 0);
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out_be32(&pcix->piwbar1, 0);
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out_be32(&pcix->piwar1, (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
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PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G));
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out_be32(&pcix->powar3, 0);
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out_be32(&pcix->powar4, 0);
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out_be32(&pcix->piwar2, 0);
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out_be32(&pcix->piwar3, 0);
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return 0;
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}
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static int mpc85xx_pci_dm_remove(struct udevice *dev)
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{
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return 0;
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}
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static int mpc85xx_pci_of_to_plat(struct udevice *dev)
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{
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struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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addr = devfdt_get_addr_index(dev, 0);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->cfg_addr = (void __iomem *)map_physmem(addr, 0, MAP_NOCACHE);
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priv->cfg_data = (void __iomem *)((ulong)priv->cfg_addr + 4);
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return 0;
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}
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static const struct dm_pci_ops mpc85xx_pci_ops = {
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.read_config = mpc85xx_pci_dm_read_config,
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.write_config = mpc85xx_pci_dm_write_config,
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};
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static const struct udevice_id mpc85xx_pci_ids[] = {
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{ .compatible = "fsl,mpc8540-pci" },
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{ }
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};
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U_BOOT_DRIVER(mpc85xx_pci) = {
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.name = "mpc85xx_pci",
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.id = UCLASS_PCI,
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.of_match = mpc85xx_pci_ids,
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.ops = &mpc85xx_pci_ops,
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.probe = mpc85xx_pci_dm_probe,
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.remove = mpc85xx_pci_dm_remove,
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.of_to_plat = mpc85xx_pci_of_to_plat,
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.priv_auto = sizeof(struct mpc85xx_pci_priv),
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};
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