mirror of
https://github.com/AsahiLinux/u-boot
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4afab721f1
Now that DM_PCI is always enabled we don't need to check it. Drop this old code. Signed-off-by: Simon Glass <sjg@chromium.org>
185 lines
4.2 KiB
C
185 lines
4.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
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*
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* Based on the Linux implementation.
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* Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
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* Authors: Carsten Langgaard <carstenl@mips.com>
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* Maciej W. Rozycki <macro@mips.com>
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*/
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#include <dm.h>
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#include <gt64120.h>
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#include <init.h>
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#include <log.h>
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#include <pci.h>
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#include <pci_gt64120.h>
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#include <asm/io.h>
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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struct gt64120_regs {
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u8 unused_000[0xc18];
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u32 intrcause;
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u8 unused_c1c[0x0dc];
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u32 pci0_cfgaddr;
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u32 pci0_cfgdata;
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};
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struct gt64120_pci_controller {
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struct pci_controller hose;
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struct gt64120_regs *regs;
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};
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static inline struct gt64120_pci_controller *
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hose_to_gt64120(struct pci_controller *hose)
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{
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return container_of(hose, struct gt64120_pci_controller, hose);
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}
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#define GT_INTRCAUSE_ABORT_BITS \
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(GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)
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static int gt_config_access(struct gt64120_pci_controller *gt,
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unsigned char access_type, pci_dev_t bdf,
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int where, u32 *data)
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{
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unsigned int bus = PCI_BUS(bdf);
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unsigned int dev = PCI_DEV(bdf);
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unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
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u32 intr;
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u32 addr;
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u32 val;
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if (bus == 0 && dev >= 31) {
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/* Because of a bug in the galileo (for slot 31). */
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return -1;
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}
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if (access_type == PCI_ACCESS_WRITE)
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debug("PCI WR %02x:%02x.%x reg:%02d data:%08x\n",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
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/* Clear cause register bits */
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writel(~GT_INTRCAUSE_ABORT_BITS, >->regs->intrcause);
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addr = GT_PCI0_CFGADDR_CONFIGEN_BIT;
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addr |= bus << GT_PCI0_CFGADDR_BUSNUM_SHF;
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addr |= devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF;
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addr |= (where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF;
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/* Setup address */
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writel(addr, >->regs->pci0_cfgaddr);
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if (access_type == PCI_ACCESS_WRITE) {
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if (bus == 0 && dev == 0) {
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/*
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* The Galileo system controller is acting
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* differently than other devices.
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*/
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val = *data;
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} else {
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val = cpu_to_le32(*data);
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}
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writel(val, >->regs->pci0_cfgdata);
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} else {
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val = readl(>->regs->pci0_cfgdata);
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if (bus == 0 && dev == 0) {
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/*
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* The Galileo system controller is acting
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* differently than other devices.
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*/
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*data = val;
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} else {
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*data = le32_to_cpu(val);
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}
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}
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/* Check for master or target abort */
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intr = readl(>->regs->intrcause);
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if (intr & GT_INTRCAUSE_ABORT_BITS) {
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/* Error occurred, clear abort bits */
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writel(~GT_INTRCAUSE_ABORT_BITS, >->regs->intrcause);
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return -1;
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}
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if (access_type == PCI_ACCESS_READ)
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debug("PCI RD %02x:%02x.%x reg:%02d data:%08x\n",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
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return 0;
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}
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static int gt64120_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
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uint where, ulong *val,
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enum pci_size_t size)
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{
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struct gt64120_pci_controller *gt = dev_get_priv(dev);
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u32 data = 0;
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if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, &data)) {
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*val = pci_get_ff(size);
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return 0;
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}
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*val = pci_conv_32_to_size(data, where, size);
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return 0;
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}
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static int gt64120_pci_write_config(struct udevice *dev, pci_dev_t bdf,
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uint where, ulong val,
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enum pci_size_t size)
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{
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struct gt64120_pci_controller *gt = dev_get_priv(dev);
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u32 data = 0;
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if (size == PCI_SIZE_32) {
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data = val;
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} else {
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u32 old;
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if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, &old))
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return 0;
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data = pci_conv_size_to_32(old, val, where, size);
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}
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gt_config_access(gt, PCI_ACCESS_WRITE, bdf, where, &data);
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return 0;
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}
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static int gt64120_pci_probe(struct udevice *dev)
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{
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struct gt64120_pci_controller *gt = dev_get_priv(dev);
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gt->regs = dev_remap_addr(dev);
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if (!gt->regs)
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return -EINVAL;
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return 0;
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}
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static const struct dm_pci_ops gt64120_pci_ops = {
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.read_config = gt64120_pci_read_config,
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.write_config = gt64120_pci_write_config,
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};
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static const struct udevice_id gt64120_pci_ids[] = {
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{ .compatible = "marvell,pci-gt64120" },
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{ }
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};
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U_BOOT_DRIVER(gt64120_pci) = {
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.name = "gt64120_pci",
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.id = UCLASS_PCI,
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.of_match = gt64120_pci_ids,
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.ops = >64120_pci_ops,
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.probe = gt64120_pci_probe,
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.priv_auto = sizeof(struct gt64120_pci_controller),
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};
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