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https://github.com/AsahiLinux/u-boot
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5690128f70
Don't know reason but in regular flow addr_hi/low are swapped in ATF. It means when fpga load is done from EL3 there is a need to swap it for PMUFW to load bitstream. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
215 lines
5 KiB
C
215 lines
5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Xilinx Zynq MPSoC Firmware driver
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*
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* Copyright (C) 2018-2019 Xilinx, Inc.
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <zynqmp_firmware.h>
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#include <asm/cache.h>
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#include <asm/ptrace.h>
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#if defined(CONFIG_ZYNQMP_IPI)
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#include <mailbox.h>
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#include <asm/arch/sys_proto.h>
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#define PMUFW_PAYLOAD_ARG_CNT 8
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#define XST_PM_NO_ACCESS 2002L
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struct zynqmp_power {
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struct mbox_chan tx_chan;
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struct mbox_chan rx_chan;
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} zynqmp_power;
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static int ipi_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen)
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{
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struct zynqmp_ipi_msg msg;
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int ret;
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if (req_len > PMUFW_PAYLOAD_ARG_CNT ||
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res_maxlen > PMUFW_PAYLOAD_ARG_CNT)
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return -EINVAL;
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if (!(zynqmp_power.tx_chan.dev) || !(&zynqmp_power.rx_chan.dev))
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return -EINVAL;
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debug("%s, Sending IPI message with ID: 0x%0x\n", __func__, req[0]);
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msg.buf = (u32 *)req;
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msg.len = req_len;
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ret = mbox_send(&zynqmp_power.tx_chan, &msg);
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if (ret) {
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debug("%s: Sending message failed\n", __func__);
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return ret;
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}
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msg.buf = res;
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msg.len = res_maxlen;
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ret = mbox_recv(&zynqmp_power.rx_chan, &msg, 100);
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if (ret)
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debug("%s: Receiving message failed\n", __func__);
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return ret;
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}
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unsigned int zynqmp_firmware_version(void)
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{
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int ret;
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u32 ret_payload[PAYLOAD_ARG_CNT];
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static u32 pm_api_version = ZYNQMP_PM_VERSION_INVALID;
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/*
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* Get PMU version only once and later
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* just return stored values instead of
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* asking PMUFW again.
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**/
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if (pm_api_version == ZYNQMP_PM_VERSION_INVALID) {
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ret = xilinx_pm_request(PM_GET_API_VERSION, 0, 0, 0, 0,
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ret_payload);
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if (ret)
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panic("PMUFW is not found - Please load it!\n");
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pm_api_version = ret_payload[1];
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if (pm_api_version < ZYNQMP_PM_VERSION)
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panic("PMUFW version error. Expected: v%d.%d\n",
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ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
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}
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return pm_api_version;
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};
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/**
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* Send a configuration object to the PMU firmware.
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*
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* @cfg_obj: Pointer to the configuration object
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* @size: Size of @cfg_obj in bytes
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*/
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void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
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{
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int err;
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u32 ret_payload[PAYLOAD_ARG_CNT];
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printf("Loading new PMUFW cfg obj (%ld bytes)\n", size);
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err = xilinx_pm_request(PM_SET_CONFIGURATION, (u32)(u64)cfg_obj, 0, 0,
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0, ret_payload);
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if (err == XST_PM_NO_ACCESS) {
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printf("PMUFW no permission to change config object\n");
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return;
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}
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if (err)
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printf("Cannot load PMUFW configuration object (%d)\n", err);
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if (ret_payload[0])
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printf("PMUFW returned 0x%08x status!\n", ret_payload[0]);
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if ((err || ret_payload[0]) && IS_ENABLED(CONFIG_SPL_BUILD))
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panic("PMUFW config object loading failed in EL3\n");
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}
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static int zynqmp_power_probe(struct udevice *dev)
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{
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int ret;
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debug("%s, (dev=%p)\n", __func__, dev);
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ret = mbox_get_by_name(dev, "tx", &zynqmp_power.tx_chan);
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if (ret) {
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debug("%s: Cannot find tx mailbox\n", __func__);
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return ret;
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}
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ret = mbox_get_by_name(dev, "rx", &zynqmp_power.rx_chan);
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if (ret) {
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debug("%s: Cannot find rx mailbox\n", __func__);
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return ret;
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}
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ret = zynqmp_firmware_version();
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printf("PMUFW:\tv%d.%d\n",
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ret >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
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ret & ZYNQMP_PM_VERSION_MINOR_MASK);
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return 0;
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};
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static const struct udevice_id zynqmp_power_ids[] = {
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{ .compatible = "xlnx,zynqmp-power" },
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{ }
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};
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U_BOOT_DRIVER(zynqmp_power) = {
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.name = "zynqmp_power",
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.id = UCLASS_FIRMWARE,
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.of_match = zynqmp_power_ids,
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.probe = zynqmp_power_probe,
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};
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#endif
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int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
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u32 arg3, u32 *ret_payload)
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{
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debug("%s at EL%d, API ID: 0x%0x\n", __func__, current_el(), api_id);
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if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
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#if defined(CONFIG_ZYNQMP_IPI)
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/*
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* Use fixed payload and arg size as the EL2 call. The firmware
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* is capable to handle PMUFW_PAYLOAD_ARG_CNT bytes but the
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* firmware API is limited by the SMC call size
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*/
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u32 regs[] = {api_id, arg0, arg1, arg2, arg3};
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if (api_id == PM_FPGA_LOAD) {
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/* Swap addr_hi/low because of incompatibility */
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u32 temp = regs[1];
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regs[1] = regs[2];
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regs[2] = temp;
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}
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ipi_req(regs, PAYLOAD_ARG_CNT, ret_payload, PAYLOAD_ARG_CNT);
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#else
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return -EPERM;
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#endif
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} else {
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/*
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* Added SIP service call Function Identifier
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* Make sure to stay in x0 register
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*/
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struct pt_regs regs;
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regs.regs[0] = PM_SIP_SVC | api_id;
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regs.regs[1] = ((u64)arg1 << 32) | arg0;
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regs.regs[2] = ((u64)arg3 << 32) | arg2;
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smc_call(®s);
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if (ret_payload) {
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ret_payload[0] = (u32)regs.regs[0];
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ret_payload[1] = upper_32_bits(regs.regs[0]);
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ret_payload[2] = (u32)regs.regs[1];
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ret_payload[3] = upper_32_bits(regs.regs[1]);
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ret_payload[4] = (u32)regs.regs[2];
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}
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}
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return (ret_payload) ? ret_payload[0] : 0;
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}
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static const struct udevice_id zynqmp_firmware_ids[] = {
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{ .compatible = "xlnx,zynqmp-firmware" },
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{ .compatible = "xlnx,versal-firmware"},
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{ }
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};
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U_BOOT_DRIVER(zynqmp_firmware) = {
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.id = UCLASS_FIRMWARE,
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.name = "zynqmp_firmware",
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.of_match = zynqmp_firmware_ids,
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};
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