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https://github.com/AsahiLinux/u-boot
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39320e7256
enable the GPMI NAND driver for i.MX8, i.MX8 use similar controller as i.MX8M - register definition for i.mx8 - DMA structure must be 32bit address Signed-off-by: Peng Fan <peng.fan@nxp.com>
116 lines
2.6 KiB
C
116 lines
2.6 KiB
C
/*
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* NXP GPMI NAND flash driver (DT initialization)
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*
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* Copyright (C) 2018 Toradex
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* Authors:
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* Stefan Agner <stefan.agner@toradex.com>
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*
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* Based on denali_dt.c
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <dm.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/printk.h>
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#include <mxs_nand.h>
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struct mxs_nand_dt_data {
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unsigned int max_ecc_strength_supported;
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};
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static const struct mxs_nand_dt_data mxs_nand_imx6q_data = {
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.max_ecc_strength_supported = 40,
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};
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static const struct mxs_nand_dt_data mxs_nand_imx6sx_data = {
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.max_ecc_strength_supported = 62,
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};
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static const struct mxs_nand_dt_data mxs_nand_imx7d_data = {
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.max_ecc_strength_supported = 62,
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};
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static const struct mxs_nand_dt_data mxs_nand_imx8qxp_data = {
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.max_ecc_strength_supported = 62,
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};
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static const struct udevice_id mxs_nand_dt_ids[] = {
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{
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.compatible = "fsl,imx6q-gpmi-nand",
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.data = (unsigned long)&mxs_nand_imx6q_data,
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},
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{
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.compatible = "fsl,imx6qp-gpmi-nand",
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.data = (unsigned long)&mxs_nand_imx6q_data,
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},
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{
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.compatible = "fsl,imx6sx-gpmi-nand",
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.data = (unsigned long)&mxs_nand_imx6sx_data,
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},
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{
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.compatible = "fsl,imx7d-gpmi-nand",
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.data = (unsigned long)&mxs_nand_imx7d_data,
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},
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{
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.compatible = "fsl,imx8qxp-gpmi-nand",
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.data = (unsigned long)&mxs_nand_imx8qxp_data,
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},
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{ /* sentinel */ }
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};
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static int mxs_nand_dt_probe(struct udevice *dev)
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{
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struct mxs_nand_info *info = dev_get_priv(dev);
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const struct mxs_nand_dt_data *data;
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struct resource res;
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int ret;
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data = (void *)dev_get_driver_data(dev);
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if (data)
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info->max_ecc_strength_supported = data->max_ecc_strength_supported;
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info->dev = dev;
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ret = dev_read_resource_byname(dev, "gpmi-nand", &res);
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if (ret)
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return ret;
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info->gpmi_regs = devm_ioremap(dev, res.start, resource_size(&res));
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ret = dev_read_resource_byname(dev, "bch", &res);
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if (ret)
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return ret;
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info->bch_regs = devm_ioremap(dev, res.start, resource_size(&res));
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info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc");
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info->legacy_bch_geometry = dev_read_bool(dev, "fsl,legacy-bch-geometry");
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return mxs_nand_init_ctrl(info);
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}
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U_BOOT_DRIVER(mxs_nand_dt) = {
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.name = "mxs-nand-dt",
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.id = UCLASS_MTD,
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.of_match = mxs_nand_dt_ids,
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.probe = mxs_nand_dt_probe,
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.priv_auto_alloc_size = sizeof(struct mxs_nand_info),
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};
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void board_nand_init(void)
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{
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struct udevice *dev;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_MTD,
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DM_GET_DRIVER(mxs_nand_dt),
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&dev);
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if (ret && ret != -ENODEV)
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pr_err("Failed to initialize MXS NAND controller. (error %d)\n",
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ret);
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}
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