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39245c8699
Based on the definitive guide to EMIF configuration[1] certain registers that we have been modifying (and are documented registers) should be left in their reset values rather than modified. This has been tested on AM335x GP EVM and Beaglebone White. [1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Javier Martinez Canillas <javier@dowhile0.org> Cc: Heiko Schocher <hs@denx.de> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Matt Porter <matt.porter@linaro.org>
462 lines
9.6 KiB
C
462 lines
9.6 KiB
C
/*
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* Board functions for TI AM335X based rut board
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* (C) Copyright 2013 Siemens Schweiz AG
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* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* Based on:
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* u-boot:/board/ti/am335x/board.c
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <spi.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <video.h>
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#include <watchdog.h>
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#include "board.h"
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#include "../common/factoryset.h"
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#include "../../../drivers/video/da8xx-fb.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Read header information from EEPROM into global structure.
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*/
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static int read_eeprom(void)
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{
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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static void board_init_ddr(void)
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{
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struct emif_regs rut_ddr3_emif_reg_data = {
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.sdram_config = 0x61C04AB2,
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.sdram_tim1 = 0x0888A39B,
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.sdram_tim2 = 0x26337FDA,
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.sdram_tim3 = 0x501F830F,
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.emif_ddr_phy_ctlr_1 = 0x6,
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.zq_config = 0x50074BE4,
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.ref_ctrl = 0x93B,
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};
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struct ddr_data rut_ddr3_data = {
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.datardsratio0 = 0x3b,
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.datawdsratio0 = 0x85,
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.datafwsratio0 = 0x100,
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.datawrsratio0 = 0xc1,
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};
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struct cmd_control rut_ddr3_cmd_ctrl_data = {
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.cmd0csratio = 0x40,
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.cmd0iclkout = 1,
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.cmd1csratio = 0x40,
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.cmd1iclkout = 1,
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.cmd2csratio = 0x40,
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.cmd2iclkout = 1,
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};
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config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data,
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&rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
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}
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static int request_and_pulse_reset(int gpio, const char *name)
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{
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int ret;
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const int delay_us = 2000; /* 2ms */
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ret = gpio_request(gpio, name);
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if (ret < 0) {
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printf("%s: Unable to request %s\n", __func__, name);
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goto err;
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}
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ret = gpio_direction_output(gpio, 0);
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if (ret < 0) {
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printf("%s: Unable to set %s as output\n", __func__, name);
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goto err_free_gpio;
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}
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udelay(delay_us);
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gpio_set_value(gpio, 1);
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return 0;
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err_free_gpio:
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gpio_free(gpio);
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err:
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return ret;
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}
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#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
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#define ETH_PHY_RESET_GPIO GPIO_TO_PIN(2, 18)
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#define MAXTOUCH_RESET_GPIO GPIO_TO_PIN(3, 18)
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#define DISPLAY_RESET_GPIO GPIO_TO_PIN(3, 19)
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#define REQUEST_AND_PULSE_RESET(N) \
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request_and_pulse_reset(N, #N);
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static void spl_siemens_board_init(void)
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{
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REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO);
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REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
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REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
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}
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#endif /* if def CONFIG_SPL_BUILD */
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#if defined(CONFIG_DRIVER_TI_CPSW)
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_id = 1,
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.phy_if = PHY_INTERFACE_MODE_RMII,
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},
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{
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.slave_reg_ofs = 0x308,
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.sliver_reg_ofs = 0xdc0,
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.phy_id = 0,
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.phy_if = PHY_INTERFACE_MODE_RMII,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x800,
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.slaves = 1,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.bd_ram_ofs = 0x2000,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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#if defined(CONFIG_DRIVER_TI_CPSW) || \
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(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
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int board_eth_init(bd_t *bis)
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{
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struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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int n = 0;
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int rv;
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#ifndef CONFIG_SPL_BUILD
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factoryset_setenv();
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#endif
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/* Set rgmii mode and enable rmii clock to be sourced from chip */
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writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
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rv = cpsw_register(&cpsw_data);
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if (rv < 0)
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printf("Error %d registering CPSW switch\n", rv);
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else
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n += rv;
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return n;
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}
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#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
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#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
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#if defined(CONFIG_HW_WATCHDOG)
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static bool hw_watchdog_init_done;
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static int hw_watchdog_trigger_level;
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void hw_watchdog_reset(void)
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{
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if (!hw_watchdog_init_done)
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return;
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hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
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gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
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}
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void hw_watchdog_init(void)
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{
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gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
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gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
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hw_watchdog_reset();
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hw_watchdog_init_done = 1;
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}
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#endif /* defined(CONFIG_HW_WATCHDOG) */
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#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
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static struct da8xx_panel lcd_panels[] = {
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/* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
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[0] = {
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.name = "KWH043MC17-F01",
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.width = 480,
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.height = 800,
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.hfp = 50, /* no spec, "don't care" values */
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.hbp = 50,
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.hsw = 50,
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.vfp = 50,
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.vbp = 50,
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.vsw = 50,
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.pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
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.invert_pxl_clk = 1,
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},
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/* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
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[1] = {
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.name = "KWH043ST20-F01",
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.width = 480,
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.height = 800,
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.hfp = 50, /* no spec, "don't care" values */
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.hbp = 50,
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.hsw = 50,
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.vfp = 50,
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.vbp = 50,
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.vsw = 50,
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.pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
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.invert_pxl_clk = 1,
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},
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/* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
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[2] = {
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.name = "MI0430VT-1",
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.width = 480,
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.height = 800,
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.hfp = 50, /* no spec, "don't care" values */
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.hbp = 50,
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.hsw = 50,
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.vfp = 50,
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.vbp = 50,
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.vsw = 50,
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.pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
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.invert_pxl_clk = 1,
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},
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};
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static const struct display_panel disp_panels[] = {
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[0] = {
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WVGA,
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16, /* RGB 888 */
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16,
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COLOR_ACTIVE,
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},
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[1] = {
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WVGA,
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16, /* RGB 888 */
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16,
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COLOR_ACTIVE,
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},
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[2] = {
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WVGA,
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24, /* RGB 888 */
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16,
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COLOR_ACTIVE,
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},
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};
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static const struct lcd_ctrl_config lcd_cfgs[] = {
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[0] = {
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&disp_panels[0],
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.ac_bias = 255,
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.ac_bias_intrpt = 0,
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.dma_burst_sz = 16,
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.bpp = 16,
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.fdd = 0x80,
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.tft_alt_mode = 0,
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.stn_565_mode = 0,
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.mono_8bit_mode = 0,
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.invert_line_clock = 1,
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.invert_frm_clock = 1,
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.sync_edge = 0,
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.sync_ctrl = 1,
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.raster_order = 0,
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},
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[1] = {
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&disp_panels[1],
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.ac_bias = 255,
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.ac_bias_intrpt = 0,
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.dma_burst_sz = 16,
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.bpp = 16,
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.fdd = 0x80,
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.tft_alt_mode = 0,
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.stn_565_mode = 0,
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.mono_8bit_mode = 0,
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.invert_line_clock = 1,
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.invert_frm_clock = 1,
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.sync_edge = 0,
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.sync_ctrl = 1,
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.raster_order = 0,
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},
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[2] = {
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&disp_panels[2],
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.ac_bias = 255,
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.ac_bias_intrpt = 0,
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.dma_burst_sz = 16,
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.bpp = 24,
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.fdd = 0x80,
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.tft_alt_mode = 0,
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.stn_565_mode = 0,
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.mono_8bit_mode = 0,
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.invert_line_clock = 1,
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.invert_frm_clock = 1,
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.sync_edge = 0,
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.sync_ctrl = 1,
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.raster_order = 0,
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},
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};
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/* no console on this board */
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int board_cfb_skip(void)
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{
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return 1;
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}
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#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
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#define PLL_GET_N(v) (v & 0x7f)
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static struct dpll_regs dpll_lcd_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x98,
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.cm_idlest_dpll = CM_WKUP + 0x48,
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.cm_clksel_dpll = CM_WKUP + 0x54,
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};
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static int get_clk(struct dpll_regs *dpll_regs)
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{
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unsigned int val;
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unsigned int m, n;
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int f = 0;
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val = readl(dpll_regs->cm_clksel_dpll);
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m = PLL_GET_M(val);
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n = PLL_GET_N(val);
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f = (m * V_OSCK) / n;
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return f;
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};
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int clk_get(int clk)
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{
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return get_clk(&dpll_lcd_regs);
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};
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static int conf_disp_pll(int m, int n)
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{
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struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
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struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
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#if defined(DISPL_PLL_SPREAD_SPECTRUM)
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struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
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#endif
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u32 *const clk_domains[] = {
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&cmper->lcdclkctrl,
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0
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};
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u32 *const clk_modules_explicit_en[] = {
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&cmper->lcdclkctrl,
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&cmper->lcdcclkstctrl,
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&cmper->spi1clkctrl,
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0
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};
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do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
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do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
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#if defined(DISPL_PLL_SPREAD_SPECTRUM)
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writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
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writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
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writel(readl(&cmwkup->clkmoddplldisp) | (1 << 12),
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&cmwkup->clkmoddplldisp); /* 0x98 */
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#endif
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return 0;
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}
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static int set_gpio(int gpio, int state)
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{
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gpio_request(gpio, "temp");
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gpio_direction_output(gpio, state);
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gpio_set_value(gpio, state);
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gpio_free(gpio);
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return 0;
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}
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static int enable_lcd(void)
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{
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unsigned char buf[1];
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set_gpio(BOARD_LCD_RESET, 0);
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mdelay(1);
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set_gpio(BOARD_LCD_RESET, 1);
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mdelay(1);
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/* spi lcd init */
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kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0);
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/* backlight on */
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buf[0] = 0xf;
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i2c_write(0x24, 0x7, 1, buf, 1);
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buf[0] = 0x3f;
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i2c_write(0x24, 0x8, 1, buf, 1);
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return 0;
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}
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int arch_early_init_r(void)
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{
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enable_lcd();
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return 0;
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}
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static int board_video_init(void)
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{
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int i;
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int anzdisp = ARRAY_SIZE(lcd_panels);
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int display = 1;
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for (i = 0; i < anzdisp; i++) {
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if (strncmp((const char *)factory_dat.disp_name,
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lcd_panels[i].name,
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strlen((const char *)factory_dat.disp_name)) == 0) {
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printf("DISPLAY: %s\n", factory_dat.disp_name);
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break;
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}
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}
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if (i == anzdisp) {
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i = 1;
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printf("%s: %s not found, using default %s\n", __func__,
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factory_dat.disp_name, lcd_panels[i].name);
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}
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conf_disp_pll(24, 1);
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da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
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lcd_cfgs[display].bpp);
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return 0;
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}
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#endif /* ifdef CONFIG_VIDEO */
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#include "../common/board.c"
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