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https://github.com/AsahiLinux/u-boot
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2df729e96d
This patch makes sure that the Devicetree for the sama5 boards are aligned with the Devicetree from Linux. This implies removing the GPIO compatible and replacing it with the PINCTRL one, as well as unifying the SDMMC pinctrl related subnodes under one single subnode. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
160 lines
3.6 KiB
Text
160 lines
3.6 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* at91-sama5d2_icp.dts - Device Tree file for SAMA5D2 ICP board
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* SAMA5D2 Industrial Connectivity Platform
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*
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* Copyright (c) 2018, Microchip Technology Inc.
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* 2018, Eugen Hristev <eugen.hristev@microchip.com>
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*/
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/dts-v1/;
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#include "sama5d2.dtsi"
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#include "sama5d2-pinfunc.h"
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/ {
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model = "Microchip SAMA5D2 ICP";
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compatible = "atmel,sama5d2-icp", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
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aliases {
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serial0 = &uart0;
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i2c1 = &i2c1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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ahb {
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sdmmc0: sdio-host@a0000000 {
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdmmc0_default>;
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status = "okay";
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};
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apb {
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qspi1: spi@f0024000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi1_sck_cs_default &pinctrl_qspi1_dat_default>;
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <83000000>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <4>;
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};
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};
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macb0: ethernet@f8008000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq &pinctrl_macb0_rst>;
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phy-mode = "internal";
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status = "okay";
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};
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uart0: serial@f801c000 { /* mikrobus1 uart */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mikrobus1_uart>;
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status = "okay";
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};
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i2c1: i2c@fc028000 {
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dmas = <0>, <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1_default>;
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status = "okay";
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eeprom@50 {
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compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */
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reg = <0x50>;
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pagesize = <16>;
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};
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eeprom@52 {
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compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */
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reg = <0x52>;
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pagesize = <16>;
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};
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eeprom@53 {
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compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */
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reg = <0x53>;
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pagesize = <16>;
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};
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};
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pioA: pinctrl@fc038000 {
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status = "okay";
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pinctrl_i2c1_default: i2c1_default {
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pinmux = <PIN_PD19__TWD1>,
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<PIN_PD20__TWCK1>;
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bias-disable;
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};
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pinctrl_macb0_rmii: macb0_rmii {
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pinmux = <PIN_PD1__GRXCK>,
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<PIN_PD2__GTXER>,
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<PIN_PD5__GRX2>,
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<PIN_PD6__GRX3>,
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<PIN_PD7__GTX2>,
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<PIN_PD8__GTX3>,
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<PIN_PD9__GTXCK>,
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<PIN_PD10__GTXEN>,
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<PIN_PD11__GRXDV>,
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<PIN_PD12__GRXER>,
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<PIN_PD13__GRX0>,
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<PIN_PD14__GRX1>,
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<PIN_PD15__GTX0>,
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<PIN_PD16__GTX1>,
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<PIN_PD17__GMDC>,
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<PIN_PD18__GMDIO>;
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bias-disable;
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};
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pinctrl_macb0_phy_irq: macb0_phy_irq {
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pinmux = <PIN_PD3__GPIO>;
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bias-disable;
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};
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pinctrl_macb0_rst: macb0_sw_rst {
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pinmux = <PIN_PD4__GPIO>;
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bias-pull-up;
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};
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pinctrl_mikrobus1_uart: mikrobus1_uart {
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pinmux = <PIN_PB26__URXD0>,
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<PIN_PB27__UTXD0>;
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bias-disable;
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};
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pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default {
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pinmux = <PIN_PA6__QSPI1_SCK>,
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<PIN_PA11__QSPI1_CS>;
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bias-disable;
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};
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pinctrl_qspi1_dat_default: qspi1_dat_default {
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pinmux = <PIN_PA7__QSPI1_IO0>,
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<PIN_PA8__QSPI1_IO1>,
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<PIN_PA9__QSPI1_IO2>,
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<PIN_PA10__QSPI1_IO3>;
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bias-pull-up;
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};
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pinctrl_sdmmc0_default: sdmmc0_default {
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pinmux = <PIN_PA1__SDMMC0_CMD>,
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<PIN_PA2__SDMMC0_DAT0>,
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<PIN_PA3__SDMMC0_DAT1>,
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<PIN_PA4__SDMMC0_DAT2>,
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<PIN_PA5__SDMMC0_DAT3>,
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<PIN_PA0__SDMMC0_CK>,
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<PIN_PA13__SDMMC0_CD>;
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bias-disable;
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};
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};
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};
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};
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};
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