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Historically the 405 U-Boot port had a dram_init() call in early init stage. This function was still called from start.S and most of the time coded in assembler. This is not needed anymore (since a long time) and boards should implement the common initdram() function in C instead. This patch now removed the dram_init() call from start.S and removes the empty implementations that are scattered through most of the 405 board ports. Some older board ports really implement this dram_init() though. These are: csb272 csb472 ERIC EXBITGEN W7OLMC W7OLMG I changed those boards to call this assembler dram_init() function now from their board specific initdram() instead. This *should* work, but please test again on those platforms. And it is perhaps a good idea that those boards use some common 405 SDRAM initialization code from cpu/ppc4xx at some time. So further patches welcome here. Signed-off-by: Stefan Roese <sr@denx.de> |
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| .. | ||
| config.mk | ||
| Makefile | ||
| mcu25.c | ||
| README.txt | ||
| u-boot.lds | ||
MCU25 Configuration Details Memory Bank 0 -- Flash chip --------------------------- 0xfff00000 - 0xffffffff The flash chip is really only 512Kbytes, but the high address bit of the 1Meg region is ignored, so the flash is replicated through the region. Thus, this is consistent with a flash base address 0xfff80000. The placement at the end is to be consistent with reset behavior, where the processor itself initially uses this bus to load the branch vector and start running. On-Chip Memory -------------- 0xf4000000 - 0xf4000fff The 405GPr includes a 4K on-chip memory that can be placed however software chooses. I choose to place the memory at this address, to keep it out of the cachable areas. Internal Peripherals -------------------- 0xef600300 - 0xef6008ff These are scattered various peripherals internal to the PPC405GPr chip. Chip-Select 2: Flash Memory --------------------------- 0x70000000 Chip-Select 3: CAN Interface ---------------------------- 0x7800000 Chip-Select 4: IMC-bus standard ------------------------------- Our IO-Bus (slow version) Chip-Select 5: IMC-bus fast (inactive) -------------------------------------- Our IO-Bus (fast, but not yet use) Memory Bank 1 -- SDRAM ------------------------------------- 0x00000000 - 0x2ffffff # Default 64 MB