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The default register configuration after powerup for PSSYSMON_ANALOG_BUS register is incorrect. Hence, fix this in SPL by writing correct fixed value. It follows UG1085 chapter 'PS SYSMON Analog_Bus' and reflects commit sw_apps:zynq ("056ca65d44549ce27f716d423e8dfdefeee7440c") in Xilinx:embeddedsw[1]. [1] https://github.com/Xilinx/embeddedsw Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
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.. | ||
include/mach | ||
clk.c | ||
cpu.c | ||
handoff.c | ||
Kconfig | ||
Makefile | ||
mkimage_fit_atf.sh | ||
mp.c | ||
psu_spl_init.c | ||
spl.c |