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https://github.com/AsahiLinux/u-boot
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38f25b125e
Errata ID:i727 Description: The refresh rate is programmed in the EMIF_SDRAM_REF_CTRL[15:0] REG_REFRESH_RATE parameter taking into account frequency of the device. When a warm reset is applied on the system, the OMAP processor restarts with another OPP and so frequency is not the same. Due to this frequency change, the refresh rate will be too low and could result in an unexpected behavior on the memory side. Workaround: The workaround is to force self-refresh when coming back from the warm reset with the following sequence: • Set EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2 • Set EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM to 0x0 • Do a dummy read (loads automatically new value of sr_tim) This will reduce the risk of memory content corruption, but memory content can't be guaranteed after a warm reset. This errata is impacted on OMAP4430: 1.0, 2.0, 2.1, 2.2, 2.3 OMAP4460: 1.0, 1.1 OMAP4470: 1.0 OMAP5430: 1.0 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
120 lines
3.6 KiB
C
120 lines
3.6 KiB
C
/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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#include <asm/arch/omap.h>
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#include <asm/io.h>
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#include <asm/arch/clocks.h>
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#include <asm/omap_common.h>
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#include <asm/arch/mux_omap5.h>
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#include <asm/arch/clocks.h>
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struct omap_sysinfo {
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char *board_string;
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};
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extern const struct omap_sysinfo sysinfo;
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void gpmc_init(void);
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void watchdog_init(void);
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u32 get_device_type(void);
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void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
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void set_muxconf_regs_essential(void);
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void set_muxconf_regs_non_essential(void);
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void sr32(void *, u32, u32, u32);
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u32 wait_on_value(u32, u32, void *, u32);
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void sdelay(unsigned long);
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void omap_rev_string(void);
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void setup_clocks_for_console(void);
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void prcm_init(void);
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void bypass_dpll(u32 *const base);
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void freq_update_core(void);
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u32 get_sys_clk_freq(void);
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u32 omap5_ddr_clk(void);
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void cancel_out(u32 *num, u32 *den, u32 den_limit);
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void sdram_init(void);
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u32 omap_sdram_size(void);
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u32 cortex_rev(void);
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void init_omap_revision(void);
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void do_io_settings(void);
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void omap_vc_init(u16 speed_khz);
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int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
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u32 warm_reset(void);
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void force_emif_self_refresh(void);
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/*
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* This is used to verify if the configuration header
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* was executed by Romcode prior to control of transfer
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* to the bootloader. SPL is responsible for saving and
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* passing this to the u-boot.
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*/
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extern struct omap_boot_parameters boot_params;
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static inline u32 running_from_sdram(void)
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{
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u32 pc;
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asm volatile ("mov %0, pc" : "=r" (pc));
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return ((pc >= OMAP54XX_DRAM_ADDR_SPACE_START) &&
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(pc < OMAP54XX_DRAM_ADDR_SPACE_END));
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}
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static inline u8 uboot_loaded_by_spl(void)
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{
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/*
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* u-boot can be running from sdram either because of configuration
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* Header or by SPL. If because of CH, then the romcode sets the
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* CHSETTINGS executed bit to true in the boot parameter structure that
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* it passes to the bootloader.This parameter is stored in the ch_flags
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* variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
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* mandatory section if CH is present.
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*/
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if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
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return 0;
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else
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return running_from_sdram();
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}
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/*
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* The basic hardware init of OMAP(s_init()) can happen in 4
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* different contexts:
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* 1. SPL running from SRAM
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* 2. U-Boot running from FLASH
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* 3. Non-XIP U-Boot loaded to SDRAM by SPL
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* 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
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* Configuration Header feature
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*
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* This function finds this context.
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* Defining as inline may help in compiling out unused functions in SPL
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*/
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static inline u32 omap_hw_init_context(void)
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{
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#ifdef CONFIG_SPL_BUILD
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return OMAP_INIT_CONTEXT_SPL;
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#else
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if (uboot_loaded_by_spl())
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return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
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else if (running_from_sdram())
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return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
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else
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return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
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#endif
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}
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#endif
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