mirror of
https://github.com/AsahiLinux/u-boot
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10ea2a7a93
Starting from QUP v2.5 the value of oversampling is changed from 32 to 16, keeping the old value on newer platforms results on wrong set UART IP clock divider, thus the asked baudrate does not correspond to the actually set with all the consequencies for a user. The change links the driver to a new Qualcomm GENI SE QUP driver to get its hardware version and update the oversampling value. Deliberately the code under CONFIG_DEBUG_UART_MSM_GENI is not touched, since a wanted baudrate can be controlled by setting a modified CONFIG_DEBUG_UART_CLOCK build time variable. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
642 lines
17 KiB
C
642 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Qualcomm GENI serial engine UART driver
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*
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* (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
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*
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* Based on Linux driver.
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*/
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#include <asm/io.h>
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <linux/delay.h>
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#include <misc.h>
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#include <serial.h>
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#define UART_OVERSAMPLING 32
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#define STALE_TIMEOUT 160
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#define USEC_PER_SEC 1000000L
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/* Registers*/
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#define GENI_FORCE_DEFAULT_REG 0x20
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#define GENI_SER_M_CLK_CFG 0x48
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#define GENI_SER_S_CLK_CFG 0x4C
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#define SE_HW_PARAM_0 0xE24
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#define SE_GENI_STATUS 0x40
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#define SE_GENI_S_CMD0 0x630
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#define SE_GENI_S_CMD_CTRL_REG 0x634
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#define SE_GENI_S_IRQ_CLEAR 0x648
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#define SE_GENI_S_IRQ_STATUS 0x640
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#define SE_GENI_S_IRQ_EN 0x644
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#define SE_GENI_M_CMD0 0x600
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#define SE_GENI_M_CMD_CTRL_REG 0x604
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#define SE_GENI_M_IRQ_CLEAR 0x618
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#define SE_GENI_M_IRQ_STATUS 0x610
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#define SE_GENI_M_IRQ_EN 0x614
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#define SE_GENI_TX_FIFOn 0x700
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#define SE_GENI_RX_FIFOn 0x780
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#define SE_GENI_TX_FIFO_STATUS 0x800
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#define SE_GENI_RX_FIFO_STATUS 0x804
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#define SE_GENI_TX_WATERMARK_REG 0x80C
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#define SE_GENI_TX_PACKING_CFG0 0x260
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#define SE_GENI_TX_PACKING_CFG1 0x264
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#define SE_GENI_RX_PACKING_CFG0 0x284
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#define SE_GENI_RX_PACKING_CFG1 0x288
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#define SE_UART_RX_STALE_CNT 0x294
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#define SE_UART_TX_TRANS_LEN 0x270
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#define SE_UART_TX_STOP_BIT_LEN 0x26c
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#define SE_UART_TX_WORD_LEN 0x268
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#define SE_UART_RX_WORD_LEN 0x28c
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#define SE_UART_TX_TRANS_CFG 0x25c
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#define SE_UART_TX_PARITY_CFG 0x2a4
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#define SE_UART_RX_TRANS_CFG 0x280
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#define SE_UART_RX_PARITY_CFG 0x2a8
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#define M_TX_FIFO_WATERMARK_EN (BIT(30))
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#define DEF_TX_WM 2
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/* GENI_FORCE_DEFAULT_REG fields */
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#define FORCE_DEFAULT (BIT(0))
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#define S_CMD_ABORT_EN (BIT(5))
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#define UART_START_READ 0x1
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/* GENI_M_CMD_CTRL_REG */
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#define M_GENI_CMD_CANCEL (BIT(2))
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#define M_GENI_CMD_ABORT (BIT(1))
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#define M_GENI_DISABLE (BIT(0))
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#define M_CMD_ABORT_EN (BIT(5))
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#define M_CMD_DONE_EN (BIT(0))
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#define M_CMD_DONE_DISABLE_MASK (~M_CMD_DONE_EN)
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#define S_GENI_CMD_ABORT (BIT(1))
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/* GENI_S_CMD0 fields */
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#define S_OPCODE_MSK (GENMASK(31, 27))
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#define S_PARAMS_MSK (GENMASK(26, 0))
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/* GENI_STATUS fields */
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#define M_GENI_CMD_ACTIVE (BIT(0))
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#define S_GENI_CMD_ACTIVE (BIT(12))
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#define M_CMD_DONE_EN (BIT(0))
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#define S_CMD_DONE_EN (BIT(0))
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#define M_OPCODE_SHIFT 27
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#define S_OPCODE_SHIFT 27
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#define M_TX_FIFO_WATERMARK_EN (BIT(30))
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#define UART_START_TX 0x1
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#define UART_CTS_MASK (BIT(1))
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#define M_SEC_IRQ_EN (BIT(31))
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#define TX_FIFO_WC_MSK (GENMASK(27, 0))
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#define RX_FIFO_WC_MSK (GENMASK(24, 0))
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#define S_RX_FIFO_WATERMARK_EN (BIT(26))
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#define S_RX_FIFO_LAST_EN (BIT(27))
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#define M_RX_FIFO_WATERMARK_EN (BIT(26))
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#define M_RX_FIFO_LAST_EN (BIT(27))
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/* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */
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#define SER_CLK_EN (BIT(0))
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#define CLK_DIV_MSK (GENMASK(15, 4))
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#define CLK_DIV_SHFT 4
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/* SE_HW_PARAM_0 fields */
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#define TX_FIFO_WIDTH_MSK (GENMASK(29, 24))
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#define TX_FIFO_WIDTH_SHFT 24
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#define TX_FIFO_DEPTH_MSK (GENMASK(21, 16))
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#define TX_FIFO_DEPTH_SHFT 16
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/* GENI SE QUP Registers */
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#define QUP_HW_VER_REG 0x4
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#define QUP_SE_VERSION_2_5 0x20050000
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/*
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* Predefined packing configuration of the serial engine (CFG0, CFG1 regs)
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* for uart mode.
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*
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* Defines following configuration:
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* - Bits of data per transfer word 8
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* - Number of words per fifo element 4
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* - Transfer from MSB to LSB or vice-versa false
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*/
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#define UART_PACKING_CFG0 0xf
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#define UART_PACKING_CFG1 0x0
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DECLARE_GLOBAL_DATA_PTR;
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struct msm_serial_data {
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phys_addr_t base;
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u32 baud;
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u32 oversampling;
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};
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unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
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32000000, 48000000, 64000000, 80000000,
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96000000, 100000000};
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/**
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* get_clk_cfg() - Get clock rate to apply on clock supplier.
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* @clk_freq: Desired clock frequency after build-in divider.
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*
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* Return: frequency, supported by clock supplier, multiple of clk_freq.
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*/
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static int get_clk_cfg(unsigned long clk_freq)
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{
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for (int i = 0; i < ARRAY_SIZE(root_freq); i++) {
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if (!(root_freq[i] % clk_freq))
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return root_freq[i];
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}
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return 0;
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}
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/**
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* get_clk_div_rate() - Find clock supplier frequency, and calculate divisor.
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* @baud: Baudrate.
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* @sampling_rate: Clock ticks per character.
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* @clk_div: Pointer to calculated divisor.
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*
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* This function searches for suitable frequency for clock supplier,
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* calculates divisor for internal divider, based on found frequency,
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* and stores divisor under clk_div pointer.
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*
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* Return: frequency, supported by clock supplier, multiple of clk_freq.
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*/
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static int get_clk_div_rate(u32 baud, u64 sampling_rate, u32 *clk_div)
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{
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unsigned long ser_clk;
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unsigned long desired_clk;
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desired_clk = baud * sampling_rate;
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ser_clk = get_clk_cfg(desired_clk);
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if (!ser_clk) {
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pr_err("%s: Can't find matching DFS entry for baud %d\n",
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__func__, baud);
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return ser_clk;
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}
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*clk_div = ser_clk / desired_clk;
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return ser_clk;
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}
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static int geni_serial_set_clock_rate(struct udevice *dev, u64 rate)
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{
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struct clk *clk;
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int ret;
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clk = devm_clk_get(dev, NULL);
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if (!clk)
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return -EINVAL;
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ret = clk_set_rate(clk, rate);
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return ret;
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}
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/**
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* geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine
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* @base: Pointer to the concerned serial engine.
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*
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* This function is used to get the depth i.e. number of elements in the
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* TX fifo of the serial engine.
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*
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* Return: TX fifo depth in units of FIFO words.
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*/
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static inline u32 geni_se_get_tx_fifo_depth(long base)
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{
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u32 tx_fifo_depth;
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tx_fifo_depth = ((readl(base + SE_HW_PARAM_0) & TX_FIFO_DEPTH_MSK) >>
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TX_FIFO_DEPTH_SHFT);
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return tx_fifo_depth;
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}
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/**
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* geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine
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* @base: Pointer to the concerned serial engine.
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*
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* This function is used to get the width i.e. word size per element in the
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* TX fifo of the serial engine.
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*
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* Return: TX fifo width in bits
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*/
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static inline u32 geni_se_get_tx_fifo_width(long base)
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{
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u32 tx_fifo_width;
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tx_fifo_width = ((readl(base + SE_HW_PARAM_0) & TX_FIFO_WIDTH_MSK) >>
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TX_FIFO_WIDTH_SHFT);
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return tx_fifo_width;
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}
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static inline void geni_serial_baud(phys_addr_t base_address, u32 clk_div,
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int baud)
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{
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u32 s_clk_cfg = 0;
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s_clk_cfg |= SER_CLK_EN;
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s_clk_cfg |= (clk_div << CLK_DIV_SHFT);
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writel(s_clk_cfg, base_address + GENI_SER_M_CLK_CFG);
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writel(s_clk_cfg, base_address + GENI_SER_S_CLK_CFG);
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}
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static int msm_serial_setbrg(struct udevice *dev, int baud)
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{
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struct msm_serial_data *priv = dev_get_priv(dev);
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u64 clk_rate;
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u32 clk_div;
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priv->baud = baud;
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clk_rate = get_clk_div_rate(baud, priv->oversampling, &clk_div);
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geni_serial_set_clock_rate(dev, clk_rate);
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geni_serial_baud(priv->base, clk_div, baud);
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return 0;
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}
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/**
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* qcom_geni_serial_poll_bit() - Poll reg bit until desired value or timeout.
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* @base: Pointer to the concerned serial engine.
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* @offset: Offset to register address.
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* @field: AND bitmask for desired bit.
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* @set: Desired bit value.
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*
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* This function is used to get the width i.e. word size per element in the
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* TX fifo of the serial engine.
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*
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* Return: true, when register bit equals desired value, false, when timeout
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* reached.
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*/
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static bool qcom_geni_serial_poll_bit(const struct udevice *dev, int offset,
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int field, bool set)
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{
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u32 reg;
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struct msm_serial_data *priv = dev_get_priv(dev);
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unsigned int baud;
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unsigned int tx_fifo_depth;
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unsigned int tx_fifo_width;
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unsigned int fifo_bits;
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unsigned long timeout_us = 10000;
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baud = 115200;
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if (priv) {
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baud = priv->baud;
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if (!baud)
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baud = 115200;
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tx_fifo_depth = geni_se_get_tx_fifo_depth(priv->base);
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tx_fifo_width = geni_se_get_tx_fifo_width(priv->base);
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fifo_bits = tx_fifo_depth * tx_fifo_width;
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/*
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* Total polling iterations based on FIFO worth of bytes to be
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* sent at current baud. Add a little fluff to the wait.
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*/
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timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
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}
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timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
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while (timeout_us) {
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reg = readl(priv->base + offset);
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if ((bool)(reg & field) == set)
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return true;
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udelay(10);
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timeout_us -= 10;
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}
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return false;
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}
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static void qcom_geni_serial_setup_tx(u64 base, u32 xmit_size)
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{
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u32 m_cmd;
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writel(xmit_size, base + SE_UART_TX_TRANS_LEN);
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m_cmd = UART_START_TX << M_OPCODE_SHIFT;
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writel(m_cmd, base + SE_GENI_M_CMD0);
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}
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static inline void qcom_geni_serial_poll_tx_done(const struct udevice *dev)
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{
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struct msm_serial_data *priv = dev_get_priv(dev);
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int done = 0;
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u32 irq_clear = M_CMD_DONE_EN;
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done = qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS,
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M_CMD_DONE_EN, true);
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if (!done) {
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writel(M_GENI_CMD_ABORT, priv->base + SE_GENI_M_CMD_CTRL_REG);
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irq_clear |= M_CMD_ABORT_EN;
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qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS,
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M_CMD_ABORT_EN, true);
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}
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writel(irq_clear, priv->base + SE_GENI_M_IRQ_CLEAR);
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}
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static u32 qcom_geni_serial_tx_empty(u64 base)
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{
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return !readl(base + SE_GENI_TX_FIFO_STATUS);
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}
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/**
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* geni_se_setup_s_cmd() - Setup the secondary sequencer
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* @se: Pointer to the concerned serial engine.
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* @cmd: Command/Operation to setup in the secondary sequencer.
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* @params: Parameter for the sequencer command.
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*
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* This function is used to configure the secondary sequencer with the
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* command and its associated parameters.
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*/
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static inline void geni_se_setup_s_cmd(u64 base, u32 cmd, u32 params)
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{
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u32 s_cmd;
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s_cmd = readl(base + SE_GENI_S_CMD0);
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s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK);
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s_cmd |= (cmd << S_OPCODE_SHIFT);
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s_cmd |= (params & S_PARAMS_MSK);
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writel(s_cmd, base + SE_GENI_S_CMD0);
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}
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static void qcom_geni_serial_start_tx(u64 base)
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{
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u32 irq_en;
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u32 status;
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status = readl(base + SE_GENI_STATUS);
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if (status & M_GENI_CMD_ACTIVE)
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return;
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if (!qcom_geni_serial_tx_empty(base))
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return;
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irq_en = readl(base + SE_GENI_M_IRQ_EN);
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irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
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writel(DEF_TX_WM, base + SE_GENI_TX_WATERMARK_REG);
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writel(irq_en, base + SE_GENI_M_IRQ_EN);
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}
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static void qcom_geni_serial_start_rx(struct udevice *dev)
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{
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u32 status;
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struct msm_serial_data *priv = dev_get_priv(dev);
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status = readl(priv->base + SE_GENI_STATUS);
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geni_se_setup_s_cmd(priv->base, UART_START_READ, 0);
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setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
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setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
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}
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static void qcom_geni_serial_abort_rx(struct udevice *dev)
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{
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struct msm_serial_data *priv = dev_get_priv(dev);
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u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
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writel(S_GENI_CMD_ABORT, priv->base + SE_GENI_S_CMD_CTRL_REG);
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qcom_geni_serial_poll_bit(dev, SE_GENI_S_CMD_CTRL_REG,
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S_GENI_CMD_ABORT, false);
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writel(irq_clear, priv->base + SE_GENI_S_IRQ_CLEAR);
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writel(FORCE_DEFAULT, priv->base + GENI_FORCE_DEFAULT_REG);
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}
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static void msm_geni_serial_setup_rx(struct udevice *dev)
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{
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struct msm_serial_data *priv = dev_get_priv(dev);
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qcom_geni_serial_abort_rx(dev);
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writel(UART_PACKING_CFG0, priv->base + SE_GENI_RX_PACKING_CFG0);
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writel(UART_PACKING_CFG1, priv->base + SE_GENI_RX_PACKING_CFG1);
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geni_se_setup_s_cmd(priv->base, UART_START_READ, 0);
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setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
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setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
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}
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static int msm_serial_putc(struct udevice *dev, const char ch)
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{
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struct msm_serial_data *priv = dev_get_priv(dev);
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writel(DEF_TX_WM, priv->base + SE_GENI_TX_WATERMARK_REG);
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qcom_geni_serial_setup_tx(priv->base, 1);
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qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS,
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M_TX_FIFO_WATERMARK_EN, true);
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writel(ch, priv->base + SE_GENI_TX_FIFOn);
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writel(M_TX_FIFO_WATERMARK_EN, priv->base + SE_GENI_M_IRQ_CLEAR);
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qcom_geni_serial_poll_tx_done(dev);
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return 0;
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}
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static int msm_serial_getc(struct udevice *dev)
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{
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struct msm_serial_data *priv = dev_get_priv(dev);
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u32 rx_fifo;
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u32 m_irq_status;
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u32 s_irq_status;
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writel(1 << S_OPCODE_SHIFT, priv->base + SE_GENI_S_CMD0);
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|
qcom_geni_serial_poll_bit(dev, SE_GENI_M_IRQ_STATUS, M_SEC_IRQ_EN,
|
|
true);
|
|
|
|
m_irq_status = readl(priv->base + SE_GENI_M_IRQ_STATUS);
|
|
s_irq_status = readl(priv->base + SE_GENI_S_IRQ_STATUS);
|
|
writel(m_irq_status, priv->base + SE_GENI_M_IRQ_CLEAR);
|
|
writel(s_irq_status, priv->base + SE_GENI_S_IRQ_CLEAR);
|
|
qcom_geni_serial_poll_bit(dev, SE_GENI_RX_FIFO_STATUS, RX_FIFO_WC_MSK,
|
|
true);
|
|
|
|
if (!readl(priv->base + SE_GENI_RX_FIFO_STATUS))
|
|
return 0;
|
|
|
|
rx_fifo = readl(priv->base + SE_GENI_RX_FIFOn);
|
|
return rx_fifo & 0xff;
|
|
}
|
|
|
|
static int msm_serial_pending(struct udevice *dev, bool input)
|
|
{
|
|
struct msm_serial_data *priv = dev_get_priv(dev);
|
|
|
|
if (input)
|
|
return readl(priv->base + SE_GENI_RX_FIFO_STATUS) &
|
|
RX_FIFO_WC_MSK;
|
|
else
|
|
return readl(priv->base + SE_GENI_TX_FIFO_STATUS) &
|
|
TX_FIFO_WC_MSK;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_serial_ops msm_serial_ops = {
|
|
.putc = msm_serial_putc,
|
|
.pending = msm_serial_pending,
|
|
.getc = msm_serial_getc,
|
|
.setbrg = msm_serial_setbrg,
|
|
};
|
|
|
|
static void geni_set_oversampling(struct udevice *dev)
|
|
{
|
|
struct msm_serial_data *priv = dev_get_priv(dev);
|
|
struct udevice *parent_dev = dev_get_parent(dev);
|
|
u32 geni_se_version;
|
|
int ret;
|
|
|
|
priv->oversampling = UART_OVERSAMPLING;
|
|
|
|
/*
|
|
* It could happen that GENI SE IP is missing in the board's device
|
|
* tree or GENI UART node is a direct child of SoC device tree node.
|
|
*/
|
|
if (device_get_uclass_id(parent_dev) != UCLASS_MISC)
|
|
return;
|
|
|
|
ret = misc_read(parent_dev, QUP_HW_VER_REG,
|
|
&geni_se_version, sizeof(geni_se_version));
|
|
if (ret != sizeof(geni_se_version))
|
|
return;
|
|
|
|
if (geni_se_version >= QUP_SE_VERSION_2_5)
|
|
priv->oversampling /= 2;
|
|
}
|
|
|
|
static inline void geni_serial_init(struct udevice *dev)
|
|
{
|
|
struct msm_serial_data *priv = dev_get_priv(dev);
|
|
phys_addr_t base_address = priv->base;
|
|
u32 tx_trans_cfg;
|
|
u32 tx_parity_cfg = 0; /* Disable Tx Parity */
|
|
u32 rx_trans_cfg = 0;
|
|
u32 rx_parity_cfg = 0; /* Disable Rx Parity */
|
|
u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
|
|
u32 bits_per_char;
|
|
|
|
/*
|
|
* Ignore Flow control.
|
|
* n = 8.
|
|
*/
|
|
tx_trans_cfg = UART_CTS_MASK;
|
|
bits_per_char = BITS_PER_BYTE;
|
|
|
|
/*
|
|
* Make an unconditional cancel on the main sequencer to reset
|
|
* it else we could end up in data loss scenarios.
|
|
*/
|
|
qcom_geni_serial_poll_tx_done(dev);
|
|
qcom_geni_serial_abort_rx(dev);
|
|
|
|
writel(UART_PACKING_CFG0, base_address + SE_GENI_TX_PACKING_CFG0);
|
|
writel(UART_PACKING_CFG1, base_address + SE_GENI_TX_PACKING_CFG1);
|
|
writel(UART_PACKING_CFG0, base_address + SE_GENI_RX_PACKING_CFG0);
|
|
writel(UART_PACKING_CFG1, base_address + SE_GENI_RX_PACKING_CFG1);
|
|
|
|
writel(tx_trans_cfg, base_address + SE_UART_TX_TRANS_CFG);
|
|
writel(tx_parity_cfg, base_address + SE_UART_TX_PARITY_CFG);
|
|
writel(rx_trans_cfg, base_address + SE_UART_RX_TRANS_CFG);
|
|
writel(rx_parity_cfg, base_address + SE_UART_RX_PARITY_CFG);
|
|
writel(bits_per_char, base_address + SE_UART_TX_WORD_LEN);
|
|
writel(bits_per_char, base_address + SE_UART_RX_WORD_LEN);
|
|
writel(stop_bit_len, base_address + SE_UART_TX_STOP_BIT_LEN);
|
|
}
|
|
|
|
static int msm_serial_probe(struct udevice *dev)
|
|
{
|
|
struct msm_serial_data *priv = dev_get_priv(dev);
|
|
|
|
geni_set_oversampling(dev);
|
|
|
|
/* No need to reinitialize the UART after relocation */
|
|
if (gd->flags & GD_FLG_RELOC)
|
|
return 0;
|
|
|
|
geni_serial_init(dev);
|
|
msm_geni_serial_setup_rx(dev);
|
|
qcom_geni_serial_start_rx(dev);
|
|
qcom_geni_serial_start_tx(priv->base);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int msm_serial_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct msm_serial_data *priv = dev_get_priv(dev);
|
|
|
|
priv->base = dev_read_addr(dev);
|
|
if (priv->base == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id msm_serial_ids[] = {
|
|
{ .compatible = "qcom,geni-debug-uart" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(serial_msm_geni) = {
|
|
.name = "serial_msm_geni",
|
|
.id = UCLASS_SERIAL,
|
|
.of_match = msm_serial_ids,
|
|
.of_to_plat = msm_serial_ofdata_to_platdata,
|
|
.priv_auto = sizeof(struct msm_serial_data),
|
|
.probe = msm_serial_probe,
|
|
.ops = &msm_serial_ops,
|
|
.flags = DM_FLAG_PRE_RELOC,
|
|
};
|
|
|
|
#ifdef CONFIG_DEBUG_UART_MSM_GENI
|
|
|
|
static struct msm_serial_data init_serial_data = {
|
|
.base = CONFIG_VAL(DEBUG_UART_BASE)
|
|
};
|
|
|
|
/* Serial dumb device, to reuse driver code */
|
|
static struct udevice init_dev = {
|
|
.priv_ = &init_serial_data,
|
|
};
|
|
|
|
#include <debug_uart.h>
|
|
|
|
#define CLK_DIV (CONFIG_DEBUG_UART_CLOCK / \
|
|
(CONFIG_BAUDRATE * UART_OVERSAMPLING))
|
|
#if (CONFIG_DEBUG_UART_CLOCK % (CONFIG_BAUDRATE * UART_OVERSAMPLING) > 0)
|
|
#error Clocks cannot be set at early debug. Change CONFIG_BAUDRATE
|
|
#endif
|
|
|
|
static inline void _debug_uart_init(void)
|
|
{
|
|
phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
|
|
|
|
geni_serial_init(&init_dev);
|
|
geni_serial_baud(base, CLK_DIV, CONFIG_BAUDRATE);
|
|
qcom_geni_serial_start_tx(base);
|
|
}
|
|
|
|
static inline void _debug_uart_putc(int ch)
|
|
{
|
|
phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
|
|
|
|
writel(DEF_TX_WM, base + SE_GENI_TX_WATERMARK_REG);
|
|
qcom_geni_serial_setup_tx(base, 1);
|
|
qcom_geni_serial_poll_bit(&init_dev, SE_GENI_M_IRQ_STATUS,
|
|
M_TX_FIFO_WATERMARK_EN, true);
|
|
|
|
writel(ch, base + SE_GENI_TX_FIFOn);
|
|
writel(M_TX_FIFO_WATERMARK_EN, base + SE_GENI_M_IRQ_CLEAR);
|
|
qcom_geni_serial_poll_tx_done(&init_dev);
|
|
}
|
|
|
|
DEBUG_UART_FUNCS
|
|
|
|
#endif
|