mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 19:10:13 +00:00
3b804b370d
Loading part of TF-A into SRAM from eMMC using DMA fails on RK3399 similar to other Rockchip SoCs. Checksum validation fails with: ## Checking hash(es) for Image atf-2 ... sha256 error! Bad hash value for 'hash' hash node in 'atf-2' image node spl_load_simple_fit: can't load image loadables index 1 (ret = -1) mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### Add a device tree property, u-boot,spl-fifo-mode, to control when the rockchip_sdhci driver should disable the use of DMA and fallback on PIO mode. Same device tree property is used by the rockchip_dw_mmc driver. In commit2cc6cde647
("mmc: rockchip_sdhci: Limit number of blocks read in a single command") the DMA mode was disabled using a CONFIG option on RK3588. Revert that and instead disable DMA using the device tree property for all RK3588 boards, also apply similar workaround for all RK3399 boards. Fixes:2cc6cde647
("mmc: rockchip_sdhci: Limit number of blocks read in a single command") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Quentin Schulz <foss+uboot@0leil.net> # RK3399 Puma, RK3588 Tiger
688 lines
19 KiB
C
688 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd
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*
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* Rockchip SD Host Controller Interface
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/ofnode.h>
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#include <dt-structs.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/libfdt.h>
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#include <linux/iopoll.h>
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#include <malloc.h>
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#include <mapmem.h>
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#include "mmc_private.h"
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#include <sdhci.h>
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#include <syscon.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/hardware.h>
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/* DWCMSHC specific Mode Select value */
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#define DWCMSHC_CTRL_HS400 0x7
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/* 400KHz is max freq for card ID etc. Use that as min */
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#define EMMC_MIN_FREQ 400000
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#define KHz (1000)
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#define MHz (1000 * KHz)
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#define SDHCI_TUNING_LOOP_COUNT 40
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#define PHYCTRL_CALDONE_MASK 0x1
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#define PHYCTRL_CALDONE_SHIFT 0x6
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#define PHYCTRL_CALDONE_DONE 0x1
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#define PHYCTRL_DLLRDY_MASK 0x1
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#define PHYCTRL_DLLRDY_SHIFT 0x5
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#define PHYCTRL_DLLRDY_DONE 0x1
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#define PHYCTRL_FREQSEL_200M 0x0
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#define PHYCTRL_FREQSEL_50M 0x1
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#define PHYCTRL_FREQSEL_100M 0x2
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#define PHYCTRL_FREQSEL_150M 0x3
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#define PHYCTRL_DLL_LOCK_WO_TMOUT(x) \
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((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\
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PHYCTRL_DLLRDY_DONE)
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#define ARASAN_VENDOR_REGISTER 0x78
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#define ARASAN_VENDOR_ENHANCED_STROBE BIT(0)
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/* Rockchip specific Registers */
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#define DWCMSHC_EMMC_EMMC_CTRL 0x52c
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#define DWCMSHC_CARD_IS_EMMC BIT(0)
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#define DWCMSHC_ENHANCED_STROBE BIT(8)
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#define DWCMSHC_EMMC_DLL_CTRL 0x800
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#define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
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#define DWCMSHC_EMMC_DLL_RXCLK 0x804
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#define DWCMSHC_EMMC_DLL_TXCLK 0x808
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#define DWCMSHC_EMMC_DLL_STRBIN 0x80c
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#define DWCMSHC_EMMC_DLL_CMDOUT 0x810
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#define DWCMSHC_EMMC_DLL_STATUS0 0x840
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#define DWCMSHC_EMMC_DLL_STATUS1 0x844
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#define DWCMSHC_EMMC_DLL_START BIT(0)
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#define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
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#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
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#define DWCMSHC_EMMC_DLL_START_POINT 16
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#define DWCMSHC_EMMC_DLL_START_DEFAULT 5
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#define DWCMSHC_EMMC_DLL_INC_VALUE 2
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#define DWCMSHC_EMMC_DLL_INC 8
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#define DWCMSHC_EMMC_DLL_BYPASS BIT(24)
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#define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
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#define DLL_RXCLK_NO_INVERTER BIT(29)
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#define DLL_RXCLK_ORI_GATE BIT(31)
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#define DLL_TXCLK_TAPNUM_DEFAULT 0x10
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#define DLL_TXCLK_TAPNUM_90_DEGREES 0x9
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#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
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#define DLL_TXCLK_NO_INVERTER BIT(29)
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#define DLL_STRBIN_TAPNUM_DEFAULT 0x4
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#define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
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#define DLL_STRBIN_DELAY_NUM_SEL BIT(26)
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#define DLL_STRBIN_DELAY_NUM_OFFSET 16
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#define DLL_STRBIN_DELAY_NUM_DEFAULT 0x10
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#define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
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#define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)
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#define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
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#define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
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#define DLL_CMDOUT_BOTH_CLK_EDGE BIT(30)
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#define DLL_LOCK_WO_TMOUT(x) \
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((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
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(((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
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#define ROCKCHIP_MAX_CLKS 3
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#define FLAG_INVERTER_FLAG_IN_RXCLK BIT(0)
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struct rockchip_sdhc_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct rockchip_emmc_phy {
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u32 emmcphy_con[7];
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u32 reserved;
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u32 emmcphy_status;
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};
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struct rockchip_sdhc {
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struct sdhci_host host;
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struct udevice *dev;
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void *base;
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struct rockchip_emmc_phy *phy;
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struct clk emmc_clk;
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};
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struct sdhci_data {
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int (*get_phy)(struct udevice *dev);
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/**
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* set_control_reg() - Set SDHCI control registers
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*
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* This is the set_control_reg() SDHCI operation that should be
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* used for the hardware this driver data is associated with.
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* Normally, this is used to set up control registers for
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* voltage level and UHS speed mode.
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*
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* @host: SDHCI host structure
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*/
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void (*set_control_reg)(struct sdhci_host *host);
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/**
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* set_ios_post() - Host specific hook after set_ios() calls
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*
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* This is the set_ios_post() SDHCI operation that should be
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* used for the hardware this driver data is associated with.
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* Normally, this is a hook that is called after sdhci_set_ios()
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* that does any necessary host-specific configuration.
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*
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* @host: SDHCI host structure
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* Return: 0 if successful, -ve on error
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*/
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int (*set_ios_post)(struct sdhci_host *host);
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void (*set_clock)(struct sdhci_host *host, u32 div);
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int (*config_dll)(struct sdhci_host *host, u32 clock, bool enable);
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/**
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* set_enhanced_strobe() - Set HS400 Enhanced Strobe config
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*
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* This is the set_enhanced_strobe() SDHCI operation that should
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* be used for the hardware this driver data is associated with.
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* Normally, this is used to set any host-specific configuration
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* necessary for HS400 ES.
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*
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* @host: SDHCI host structure
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* Return: 0 if successful, -ve on error
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*/
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int (*set_enhanced_strobe)(struct sdhci_host *host);
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u32 flags;
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u8 hs200_txclk_tapnum;
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u8 hs400_txclk_tapnum;
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};
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static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
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{
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u32 caldone, dllrdy, freqsel;
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writel(RK_CLRSETBITS(7 << 4, 0), &phy->emmcphy_con[6]);
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writel(RK_CLRSETBITS(1 << 11, 1 << 11), &phy->emmcphy_con[0]);
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writel(RK_CLRSETBITS(0xf << 7, 6 << 7), &phy->emmcphy_con[0]);
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/*
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* According to the user manual, calpad calibration
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* cycle takes more than 2us without the minimal recommended
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* value, so we may need a little margin here
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*/
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udelay(3);
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writel(RK_CLRSETBITS(1, 1), &phy->emmcphy_con[6]);
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/*
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* According to the user manual, it asks driver to
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* wait 5us for calpad busy trimming. But it seems that
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* 5us of caldone isn't enough for all cases.
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*/
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udelay(500);
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caldone = readl(&phy->emmcphy_status);
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caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
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if (caldone != PHYCTRL_CALDONE_DONE) {
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printf("%s: caldone timeout.\n", __func__);
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return;
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}
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/* Set the frequency of the DLL operation */
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if (clock < 75 * MHz)
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freqsel = PHYCTRL_FREQSEL_50M;
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else if (clock < 125 * MHz)
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freqsel = PHYCTRL_FREQSEL_100M;
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else if (clock < 175 * MHz)
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freqsel = PHYCTRL_FREQSEL_150M;
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else
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freqsel = PHYCTRL_FREQSEL_200M;
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/* Set the frequency of the DLL operation */
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writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]);
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writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]);
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/* REN Enable on STRB Line for HS400 */
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writel(RK_CLRSETBITS(0, 1 << 9), &phy->emmcphy_con[2]);
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read_poll_timeout(readl, dllrdy, PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1,
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5000, &phy->emmcphy_status);
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}
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static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy)
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{
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writel(RK_CLRSETBITS(1, 0), &phy->emmcphy_con[6]);
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writel(RK_CLRSETBITS(1 << 1, 0), &phy->emmcphy_con[6]);
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}
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static int rk3399_emmc_get_phy(struct udevice *dev)
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{
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struct rockchip_sdhc *priv = dev_get_priv(dev);
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ofnode phy_node;
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void *grf_base;
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u32 grf_phy_offset, phandle;
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phandle = dev_read_u32_default(dev, "phys", 0);
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phy_node = ofnode_get_by_phandle(phandle);
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if (!ofnode_valid(phy_node)) {
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debug("Not found emmc phy device\n");
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return -ENODEV;
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}
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grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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if (IS_ERR_OR_NULL(grf_base)) {
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printf("%s Get syscon grf failed", __func__);
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return -ENODEV;
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}
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grf_phy_offset = ofnode_read_u32_default(phy_node, "reg", 0);
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priv->phy = (struct rockchip_emmc_phy *)(grf_base + grf_phy_offset);
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return 0;
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}
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static int rk3399_sdhci_set_enhanced_strobe(struct sdhci_host *host)
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{
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struct mmc *mmc = host->mmc;
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u32 vendor;
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vendor = sdhci_readl(host, ARASAN_VENDOR_REGISTER);
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if (mmc->selected_mode == MMC_HS_400_ES)
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vendor |= ARASAN_VENDOR_ENHANCED_STROBE;
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else
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vendor &= ~ARASAN_VENDOR_ENHANCED_STROBE;
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sdhci_writel(host, vendor, ARASAN_VENDOR_REGISTER);
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return 0;
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}
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static void rk3399_sdhci_set_control_reg(struct sdhci_host *host)
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{
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struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
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struct mmc *mmc = host->mmc;
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uint clock = mmc->tran_speed;
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int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ;
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if (cycle_phy)
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rk3399_emmc_phy_power_off(priv->phy);
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sdhci_set_control_reg(host);
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/*
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* Reinitializing the device tries to set it to lower-speed modes
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* first, which fails if the Enhanced Strobe bit is set, making
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* the device impossible to use. Set the correct value here to
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* let reinitialization attempts succeed.
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*/
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if (CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT))
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rk3399_sdhci_set_enhanced_strobe(host);
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};
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static int rk3399_sdhci_set_ios_post(struct sdhci_host *host)
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{
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struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
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struct mmc *mmc = host->mmc;
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uint clock = mmc->tran_speed;
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int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ;
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if (!clock)
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clock = mmc->clock;
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if (cycle_phy)
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rk3399_emmc_phy_power_on(priv->phy, clock);
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return 0;
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}
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static void rk3568_sdhci_set_clock(struct sdhci_host *host, u32 div)
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{
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struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
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struct mmc *mmc = host->mmc;
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ulong rate;
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rate = clk_set_rate(&priv->emmc_clk, mmc->clock);
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if (IS_ERR_VALUE(rate))
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printf("%s: Set clock rate failed: %ld\n", __func__, (long)rate);
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}
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static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enable)
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{
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struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
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struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
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struct mmc *mmc = host->mmc;
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int val, ret;
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u32 extra, txclk_tapnum;
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if (!enable)
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return 0;
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if (clock >= 100 * MHz) {
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/* reset DLL */
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sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL);
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udelay(1);
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sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
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/* Init DLL settings */
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extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT |
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DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC |
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DWCMSHC_EMMC_DLL_START;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
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ret = read_poll_timeout(readl, val, DLL_LOCK_WO_TMOUT(val), 1,
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500,
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host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0);
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if (ret)
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return ret;
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extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_ORI_GATE;
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if (data->flags & FLAG_INVERTER_FLAG_IN_RXCLK)
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extra |= DLL_RXCLK_NO_INVERTER;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
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txclk_tapnum = data->hs200_txclk_tapnum;
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if (mmc->selected_mode == MMC_HS_400 ||
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mmc->selected_mode == MMC_HS_400_ES) {
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txclk_tapnum = data->hs400_txclk_tapnum;
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extra = DLL_CMDOUT_SRC_CLK_NEG |
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DLL_CMDOUT_BOTH_CLK_EDGE |
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DWCMSHC_EMMC_DLL_DLYENA |
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DLL_CMDOUT_TAPNUM_90_DEGREES |
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DLL_CMDOUT_TAPNUM_FROM_SW;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CMDOUT);
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}
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extra = DWCMSHC_EMMC_DLL_DLYENA |
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DLL_TXCLK_TAPNUM_FROM_SW |
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DLL_TXCLK_NO_INVERTER |
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txclk_tapnum;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
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extra = DWCMSHC_EMMC_DLL_DLYENA |
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DLL_STRBIN_TAPNUM_DEFAULT |
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DLL_STRBIN_TAPNUM_FROM_SW;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
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} else {
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/*
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* Disable DLL and reset both of sample and drive clock.
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* The bypass bit and start bit need to be set if DLL is not locked.
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*/
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extra = DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
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sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
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sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
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sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CMDOUT);
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/*
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* Before switching to hs400es mode, the driver will enable
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* enhanced strobe first. PHY needs to configure the parameters
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* of enhanced strobe first.
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*/
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extra = DWCMSHC_EMMC_DLL_DLYENA |
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DLL_STRBIN_DELAY_NUM_SEL |
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DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
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}
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return 0;
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}
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static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
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{
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struct mmc *mmc = host->mmc;
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u32 reg;
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reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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reg &= ~SDHCI_CTRL_UHS_MASK;
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switch (mmc->selected_mode) {
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case UHS_SDR25:
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case MMC_HS:
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case MMC_HS_52:
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reg |= SDHCI_CTRL_UHS_SDR25;
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break;
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case UHS_SDR50:
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reg |= SDHCI_CTRL_UHS_SDR50;
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break;
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case UHS_DDR50:
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case MMC_DDR_52:
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reg |= SDHCI_CTRL_UHS_DDR50;
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break;
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case UHS_SDR104:
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case MMC_HS_200:
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reg |= SDHCI_CTRL_UHS_SDR104;
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break;
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case MMC_HS_400:
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case MMC_HS_400_ES:
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reg |= DWCMSHC_CTRL_HS400;
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break;
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default:
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reg |= SDHCI_CTRL_UHS_SDR12;
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}
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sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
|
|
|
|
reg = sdhci_readw(host, DWCMSHC_EMMC_EMMC_CTRL);
|
|
|
|
if (IS_MMC(mmc))
|
|
reg |= DWCMSHC_CARD_IS_EMMC;
|
|
else
|
|
reg &= ~DWCMSHC_CARD_IS_EMMC;
|
|
|
|
if (mmc->selected_mode == MMC_HS_400_ES)
|
|
reg |= DWCMSHC_ENHANCED_STROBE;
|
|
else
|
|
reg &= ~DWCMSHC_ENHANCED_STROBE;
|
|
|
|
sdhci_writew(host, reg, DWCMSHC_EMMC_EMMC_CTRL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void rockchip_sdhci_set_control_reg(struct sdhci_host *host)
|
|
{
|
|
struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
|
|
struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
|
|
|
|
if (data->set_control_reg)
|
|
data->set_control_reg(host);
|
|
}
|
|
|
|
static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
|
|
{
|
|
struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
|
|
struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
|
|
|
|
if (data->set_ios_post)
|
|
return data->set_ios_post(host);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void rockchip_sdhci_set_clock(struct sdhci_host *host, u32 div)
|
|
{
|
|
struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
|
|
struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
|
|
|
|
if (data->set_clock)
|
|
data->set_clock(host, div);
|
|
}
|
|
|
|
static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
|
|
{
|
|
struct rockchip_sdhc *priv = dev_get_priv(mmc->dev);
|
|
struct sdhci_host *host = &priv->host;
|
|
char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
|
|
struct mmc_cmd cmd;
|
|
u32 ctrl, blk_size;
|
|
int ret;
|
|
|
|
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
|
|
ctrl |= SDHCI_CTRL_EXEC_TUNING;
|
|
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
|
|
|
|
sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
|
|
|
|
blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64);
|
|
if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8)
|
|
blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128);
|
|
sdhci_writew(host, blk_size, SDHCI_BLOCK_SIZE);
|
|
sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
|
|
|
|
cmd.cmdidx = opcode;
|
|
cmd.resp_type = MMC_RSP_R1;
|
|
cmd.cmdarg = 0;
|
|
|
|
do {
|
|
ret = mmc_send_cmd(mmc, &cmd, NULL);
|
|
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
|
|
if (ret || tuning_loop_counter-- == 0)
|
|
break;
|
|
} while (ctrl & SDHCI_CTRL_EXEC_TUNING);
|
|
|
|
if (ret || tuning_loop_counter < 0 || !(ctrl & SDHCI_CTRL_TUNED_CLK)) {
|
|
if (!ret)
|
|
ret = -EIO;
|
|
printf("%s: Tuning failed: %d\n", __func__, ret);
|
|
|
|
ctrl &= ~SDHCI_CTRL_TUNED_CLK;
|
|
ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
|
|
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
|
|
}
|
|
|
|
/* Enable only interrupts served by the SD controller */
|
|
sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, SDHCI_INT_ENABLE);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rockchip_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enable)
|
|
{
|
|
struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
|
|
struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
|
|
|
|
if (data->config_dll)
|
|
return data->config_dll(host, clock, enable);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_sdhci_set_enhanced_strobe(struct sdhci_host *host)
|
|
{
|
|
struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
|
|
struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
|
|
|
|
if (data->set_enhanced_strobe)
|
|
return data->set_enhanced_strobe(host);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct sdhci_ops rockchip_sdhci_ops = {
|
|
.set_control_reg = rockchip_sdhci_set_control_reg,
|
|
.set_ios_post = rockchip_sdhci_set_ios_post,
|
|
.set_clock = rockchip_sdhci_set_clock,
|
|
.platform_execute_tuning = rockchip_sdhci_execute_tuning,
|
|
.config_dll = rockchip_sdhci_config_dll,
|
|
.set_enhanced_strobe = rockchip_sdhci_set_enhanced_strobe,
|
|
};
|
|
|
|
static int rockchip_sdhci_probe(struct udevice *dev)
|
|
{
|
|
struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev);
|
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
|
struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
|
|
struct rockchip_sdhc *priv = dev_get_priv(dev);
|
|
struct mmc_config *cfg = &plat->cfg;
|
|
struct sdhci_host *host = &priv->host;
|
|
struct clk clk;
|
|
int ret;
|
|
|
|
host->max_clk = cfg->f_max;
|
|
ret = clk_get_by_index(dev, 0, &clk);
|
|
if (!ret) {
|
|
ret = clk_set_rate(&clk, host->max_clk);
|
|
if (IS_ERR_VALUE(ret))
|
|
printf("%s clk set rate fail!\n", __func__);
|
|
} else {
|
|
printf("%s fail to get clk\n", __func__);
|
|
}
|
|
|
|
priv->emmc_clk = clk;
|
|
priv->dev = dev;
|
|
|
|
if (data->get_phy) {
|
|
ret = data->get_phy(dev);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
host->ops = &rockchip_sdhci_ops;
|
|
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
|
|
|
|
host->mmc = &plat->mmc;
|
|
host->mmc->priv = &priv->host;
|
|
host->mmc->dev = dev;
|
|
upriv->mmc = host->mmc;
|
|
|
|
ret = sdhci_setup_cfg(cfg, host, cfg->f_max, EMMC_MIN_FREQ);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* Disable use of DMA and force use of PIO mode in SPL to fix an issue
|
|
* where loading part of TF-A into SRAM using DMA silently fails.
|
|
*/
|
|
if (IS_ENABLED(CONFIG_SPL_BUILD) &&
|
|
dev_read_bool(dev, "u-boot,spl-fifo-mode"))
|
|
host->flags &= ~USE_DMA;
|
|
|
|
/*
|
|
* Reading more than 4 blocks with a single CMD18 command in PIO mode
|
|
* triggers Data End Bit Error on RK3568 and RK3588. Limit to reading
|
|
* max 4 blocks in one command when using PIO mode.
|
|
*/
|
|
if (!(host->flags & USE_DMA) &&
|
|
(device_is_compatible(dev, "rockchip,rk3568-dwcmshc") ||
|
|
device_is_compatible(dev, "rockchip,rk3588-dwcmshc")))
|
|
cfg->b_max = 4;
|
|
|
|
return sdhci_probe(dev);
|
|
}
|
|
|
|
static int rockchip_sdhci_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
|
|
struct rockchip_sdhc *priv = dev_get_priv(dev);
|
|
struct mmc_config *cfg = &plat->cfg;
|
|
struct sdhci_host *host = &priv->host;
|
|
int ret;
|
|
|
|
host->name = dev->name;
|
|
host->ioaddr = dev_read_addr_ptr(dev);
|
|
|
|
ret = mmc_of_parse(dev, cfg);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_sdhci_bind(struct udevice *dev)
|
|
{
|
|
struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
|
|
|
|
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
|
|
}
|
|
|
|
static const struct sdhci_data rk3399_data = {
|
|
.get_phy = rk3399_emmc_get_phy,
|
|
.set_control_reg = rk3399_sdhci_set_control_reg,
|
|
.set_ios_post = rk3399_sdhci_set_ios_post,
|
|
.set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe,
|
|
};
|
|
|
|
static const struct sdhci_data rk3568_data = {
|
|
.set_ios_post = rk3568_sdhci_set_ios_post,
|
|
.set_clock = rk3568_sdhci_set_clock,
|
|
.config_dll = rk3568_sdhci_config_dll,
|
|
.flags = FLAG_INVERTER_FLAG_IN_RXCLK,
|
|
.hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
|
|
.hs400_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
|
|
};
|
|
|
|
static const struct sdhci_data rk3588_data = {
|
|
.set_ios_post = rk3568_sdhci_set_ios_post,
|
|
.set_clock = rk3568_sdhci_set_clock,
|
|
.config_dll = rk3568_sdhci_config_dll,
|
|
.hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
|
|
.hs400_txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES,
|
|
};
|
|
|
|
static const struct udevice_id sdhci_ids[] = {
|
|
{
|
|
.compatible = "arasan,sdhci-5.1",
|
|
.data = (ulong)&rk3399_data,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3568-dwcmshc",
|
|
.data = (ulong)&rk3568_data,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3588-dwcmshc",
|
|
.data = (ulong)&rk3588_data,
|
|
},
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(arasan_sdhci_drv) = {
|
|
.name = "rockchip_sdhci_5_1",
|
|
.id = UCLASS_MMC,
|
|
.of_match = sdhci_ids,
|
|
.of_to_plat = rockchip_sdhci_of_to_plat,
|
|
.ops = &sdhci_ops,
|
|
.bind = rockchip_sdhci_bind,
|
|
.probe = rockchip_sdhci_probe,
|
|
.priv_auto = sizeof(struct rockchip_sdhc),
|
|
.plat_auto = sizeof(struct rockchip_sdhc_plat),
|
|
};
|