mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 19:10:13 +00:00
a12a73b664
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use dev_read_addr_ptr instead of the dev_read_addr function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
543 lines
14 KiB
C
543 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Davinci MMC Controller Driver
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*
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* Copyright (C) 2010 Texas Instruments Incorporated
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*/
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#include <config.h>
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <mmc.h>
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#include <command.h>
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#include <part.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/arch/sdmmc_defs.h>
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#include <asm-generic/gpio.h>
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#include <linux/delay.h>
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#define WATCHDOG_COUNT (100000)
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#define get_val(addr) REG(addr)
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#define set_val(addr, val) REG(addr) = (val)
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#define set_bit(addr, val) set_val((addr), (get_val(addr) | (val)))
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#define clear_bit(addr, val) set_val((addr), (get_val(addr) & ~(val)))
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#ifdef CONFIG_DM_MMC
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/* Davinci MMC board definitions */
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struct davinci_mmc_priv {
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struct davinci_mmc_regs *reg_base; /* Register base address */
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uint input_clk; /* Input clock to MMC controller */
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struct gpio_desc cd_gpio; /* Card Detect GPIO */
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struct gpio_desc wp_gpio; /* Write Protect GPIO */
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};
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#endif
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/* Set davinci clock prescalar value based on the required clock in HZ */
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#if !CONFIG_IS_ENABLED(DM_MMC)
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static void dmmc_set_clock(struct mmc *mmc, uint clock)
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{
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struct davinci_mmc *host = mmc->priv;
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#else
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static void davinci_mmc_set_clock(struct udevice *dev, uint clock)
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{
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struct davinci_mmc_priv *host = dev_get_priv(dev);
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struct mmc *mmc = mmc_get_mmc_dev(dev);
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#endif
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struct davinci_mmc_regs *regs = host->reg_base;
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uint clkrt, sysclk2, act_clock;
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if (clock < mmc->cfg->f_min)
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clock = mmc->cfg->f_min;
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if (clock > mmc->cfg->f_max)
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clock = mmc->cfg->f_max;
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set_val(®s->mmcclk, 0);
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sysclk2 = host->input_clk;
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clkrt = (sysclk2 / (2 * clock)) - 1;
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/* Calculate the actual clock for the divider used */
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act_clock = (sysclk2 / (2 * (clkrt + 1)));
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/* Adjust divider if actual clock exceeds the required clock */
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if (act_clock > clock)
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clkrt++;
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/* check clock divider boundary and correct it */
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if (clkrt > 0xFF)
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clkrt = 0xFF;
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set_val(®s->mmcclk, (clkrt | MMCCLK_CLKEN));
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}
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/* Status bit wait loop for MMCST1 */
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static int
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dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status)
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{
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uint wdog = WATCHDOG_COUNT;
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while (--wdog && ((get_val(®s->mmcst1) & status) != status))
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udelay(10);
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if (!(get_val(®s->mmcctl) & MMCCTL_WIDTH_4_BIT))
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udelay(100);
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if (wdog == 0)
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return -ECOMM;
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return 0;
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}
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/* Busy bit wait loop for MMCST1 */
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static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs)
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{
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uint wdog = WATCHDOG_COUNT;
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while (--wdog && (get_val(®s->mmcst1) & MMCST1_BUSY))
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udelay(10);
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if (wdog == 0)
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return -ECOMM;
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return 0;
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}
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/* Status bit wait loop for MMCST0 - Checks for error bits as well */
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static int dmmc_check_status(volatile struct davinci_mmc_regs *regs,
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uint *cur_st, uint st_ready, uint st_error)
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{
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uint wdog = WATCHDOG_COUNT;
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uint mmcstatus = *cur_st;
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while (wdog--) {
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if (mmcstatus & st_ready) {
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*cur_st = mmcstatus;
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mmcstatus = get_val(®s->mmcst1);
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return 0;
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} else if (mmcstatus & st_error) {
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if (mmcstatus & MMCST0_TOUTRS)
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return -ETIMEDOUT;
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printf("[ ST0 ERROR %x]\n", mmcstatus);
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/*
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* Ignore CRC errors as some MMC cards fail to
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* initialize on DM365-EVM on the SD1 slot
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*/
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if (mmcstatus & MMCST0_CRCRS)
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return 0;
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return -ECOMM;
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}
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udelay(10);
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mmcstatus = get_val(®s->mmcst0);
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}
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printf("Status %x Timeout ST0:%x ST1:%x\n", st_ready, mmcstatus,
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get_val(®s->mmcst1));
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return -ECOMM;
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}
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/*
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* Sends a command out on the bus. Takes the device pointer,
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* a command pointer, and an optional data pointer.
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*/
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#if !CONFIG_IS_ENABLED(DM_MMC)
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static int dmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
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{
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struct davinci_mmc *host = mmc->priv;
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#else
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static int
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davinci_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
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{
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struct davinci_mmc_priv *host = dev_get_priv(dev);
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#endif
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volatile struct davinci_mmc_regs *regs = host->reg_base;
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uint mmcstatus, status_rdy, status_err;
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uint i, cmddata, bytes_left = 0;
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int fifo_words, fifo_bytes, err;
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char *data_buf = NULL;
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/* Clear status registers */
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mmcstatus = get_val(®s->mmcst0);
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fifo_words = 16;
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fifo_bytes = fifo_words << 2;
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/* Wait for any previous busy signal to be cleared */
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dmmc_busy_wait(regs);
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cmddata = cmd->cmdidx;
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cmddata |= MMCCMD_PPLEN;
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/* Send init clock for CMD0 */
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if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE)
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cmddata |= MMCCMD_INITCK;
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switch (cmd->resp_type) {
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case MMC_RSP_R1b:
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cmddata |= MMCCMD_BSYEXP;
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/* Fall-through */
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case MMC_RSP_R1: /* R1, R1b, R5, R6, R7 */
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cmddata |= MMCCMD_RSPFMT_R1567;
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break;
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case MMC_RSP_R2:
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cmddata |= MMCCMD_RSPFMT_R2;
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break;
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case MMC_RSP_R3: /* R3, R4 */
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cmddata |= MMCCMD_RSPFMT_R3;
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break;
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}
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set_val(®s->mmcim, 0);
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if (data) {
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/* clear previous data transfer if any and set new one */
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bytes_left = (data->blocksize * data->blocks);
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/* Reset FIFO - Always use 32 byte fifo threshold */
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set_val(®s->mmcfifoctl,
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(MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
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cmddata |= MMCCMD_DMATRIG;
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cmddata |= MMCCMD_WDATX;
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if (data->flags == MMC_DATA_READ) {
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set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
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} else if (data->flags == MMC_DATA_WRITE) {
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set_val(®s->mmcfifoctl,
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(MMCFIFOCTL_FIFOLEV |
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MMCFIFOCTL_FIFODIR));
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cmddata |= MMCCMD_DTRW;
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}
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set_val(®s->mmctod, 0xFFFF);
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set_val(®s->mmcnblk, (data->blocks & MMCNBLK_NBLK_MASK));
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set_val(®s->mmcblen, (data->blocksize & MMCBLEN_BLEN_MASK));
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if (data->flags == MMC_DATA_WRITE) {
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uint val;
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data_buf = (char *)data->src;
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/* For write, fill FIFO with data before issue of CMD */
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for (i = 0; (i < fifo_words) && bytes_left; i++) {
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memcpy((char *)&val, data_buf, 4);
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set_val(®s->mmcdxr, val);
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data_buf += 4;
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bytes_left -= 4;
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}
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}
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} else {
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set_val(®s->mmcblen, 0);
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set_val(®s->mmcnblk, 0);
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}
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set_val(®s->mmctor, 0x1FFF);
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/* Send the command */
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set_val(®s->mmcarghl, cmd->cmdarg);
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set_val(®s->mmccmd, cmddata);
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status_rdy = MMCST0_RSPDNE;
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status_err = (MMCST0_TOUTRS | MMCST0_TOUTRD |
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MMCST0_CRCWR | MMCST0_CRCRD);
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if (cmd->resp_type & MMC_RSP_CRC)
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status_err |= MMCST0_CRCRS;
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mmcstatus = get_val(®s->mmcst0);
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err = dmmc_check_status(regs, &mmcstatus, status_rdy, status_err);
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if (err)
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return err;
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/* For R1b wait for busy done */
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if (cmd->resp_type == MMC_RSP_R1b)
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dmmc_busy_wait(regs);
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/* Collect response from controller for specific commands */
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if (mmcstatus & MMCST0_RSPDNE) {
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/* Copy the response to the response buffer */
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if (cmd->resp_type & MMC_RSP_136) {
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cmd->response[0] = get_val(®s->mmcrsp67);
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cmd->response[1] = get_val(®s->mmcrsp45);
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cmd->response[2] = get_val(®s->mmcrsp23);
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cmd->response[3] = get_val(®s->mmcrsp01);
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} else if (cmd->resp_type & MMC_RSP_PRESENT) {
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cmd->response[0] = get_val(®s->mmcrsp67);
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}
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}
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if (data == NULL)
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return 0;
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if (data->flags == MMC_DATA_READ) {
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/* check for DATDNE along with DRRDY as the controller might
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* set the DATDNE without DRRDY for smaller transfers with
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* less than FIFO threshold bytes
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*/
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status_rdy = MMCST0_DRRDY | MMCST0_DATDNE;
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status_err = MMCST0_TOUTRD | MMCST0_CRCRD;
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data_buf = data->dest;
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} else {
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status_rdy = MMCST0_DXRDY | MMCST0_DATDNE;
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status_err = MMCST0_CRCWR;
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}
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/* Wait until all of the blocks are transferred */
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while (bytes_left) {
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err = dmmc_check_status(regs, &mmcstatus, status_rdy,
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status_err);
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if (err)
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return err;
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if (data->flags == MMC_DATA_READ) {
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/*
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* MMC controller sets the Data receive ready bit
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* (DRRDY) in MMCST0 even before the entire FIFO is
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* full. This results in erratic behavior if we start
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* reading the FIFO soon after DRRDY. Wait for the
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* FIFO full bit in MMCST1 for proper FIFO clearing.
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*/
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if (bytes_left > fifo_bytes)
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dmmc_wait_fifo_status(regs, 0x4a);
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else if (bytes_left == fifo_bytes) {
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dmmc_wait_fifo_status(regs, 0x40);
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if (cmd->cmdidx == MMC_CMD_SEND_EXT_CSD)
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udelay(600);
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}
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for (i = 0; bytes_left && (i < fifo_words); i++) {
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cmddata = get_val(®s->mmcdrr);
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memcpy(data_buf, (char *)&cmddata, 4);
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data_buf += 4;
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bytes_left -= 4;
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}
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} else {
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/*
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* MMC controller sets the Data transmit ready bit
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* (DXRDY) in MMCST0 even before the entire FIFO is
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* empty. This results in erratic behavior if we start
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* writing the FIFO soon after DXRDY. Wait for the
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* FIFO empty bit in MMCST1 for proper FIFO clearing.
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*/
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dmmc_wait_fifo_status(regs, MMCST1_FIFOEMP);
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for (i = 0; bytes_left && (i < fifo_words); i++) {
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memcpy((char *)&cmddata, data_buf, 4);
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set_val(®s->mmcdxr, cmddata);
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data_buf += 4;
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bytes_left -= 4;
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}
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dmmc_busy_wait(regs);
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}
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}
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err = dmmc_check_status(regs, &mmcstatus, MMCST0_DATDNE, status_err);
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if (err)
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return err;
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return 0;
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}
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/* Initialize Davinci MMC controller */
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#if !CONFIG_IS_ENABLED(DM_MMC)
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static int dmmc_init(struct mmc *mmc)
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{
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struct davinci_mmc *host = mmc->priv;
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#else
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static int davinci_dm_mmc_init(struct udevice *dev)
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{
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struct davinci_mmc_priv *host = dev_get_priv(dev);
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#endif
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struct davinci_mmc_regs *regs = host->reg_base;
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/* Clear status registers explicitly - soft reset doesn't clear it
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* If Uboot is invoked from UBL with SDMMC Support, the status
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* registers can have uncleared bits
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*/
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get_val(®s->mmcst0);
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get_val(®s->mmcst1);
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/* Hold software reset */
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set_bit(®s->mmcctl, MMCCTL_DATRST);
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set_bit(®s->mmcctl, MMCCTL_CMDRST);
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udelay(10);
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set_val(®s->mmcclk, 0x0);
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set_val(®s->mmctor, 0x1FFF);
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set_val(®s->mmctod, 0xFFFF);
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/* Clear software reset */
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clear_bit(®s->mmcctl, MMCCTL_DATRST);
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clear_bit(®s->mmcctl, MMCCTL_CMDRST);
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udelay(10);
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/* Reset FIFO - Always use the maximum fifo threshold */
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set_val(®s->mmcfifoctl, (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
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set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
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return 0;
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}
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/* Set buswidth or clock as indicated by the MMC framework */
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#if !CONFIG_IS_ENABLED(DM_MMC)
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static int dmmc_set_ios(struct mmc *mmc)
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{
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struct davinci_mmc *host = mmc->priv;
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struct davinci_mmc_regs *regs = host->reg_base;
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#else
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static int davinci_mmc_set_ios(struct udevice *dev)
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{
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struct mmc *mmc = mmc_get_mmc_dev(dev);
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struct davinci_mmc_priv *host = dev_get_priv(dev);
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struct davinci_mmc_regs *regs = host->reg_base;
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#endif
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/* Set the bus width */
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if (mmc->bus_width == 4)
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set_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT);
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else
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clear_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT);
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/* Set clock speed */
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if (mmc->clock) {
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#if !CONFIG_IS_ENABLED(DM_MMC)
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dmmc_set_clock(mmc, mmc->clock);
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#else
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davinci_mmc_set_clock(dev, mmc->clock);
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#endif
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}
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return 0;
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}
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#if !CONFIG_IS_ENABLED(DM_MMC)
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static const struct mmc_ops dmmc_ops = {
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.send_cmd = dmmc_send_cmd,
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.set_ios = dmmc_set_ios,
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.init = dmmc_init,
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};
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#else
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static int davinci_mmc_getcd(struct udevice *dev)
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{
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int value = -1;
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#if CONFIG_IS_ENABLED(DM_GPIO)
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struct davinci_mmc_priv *priv = dev_get_priv(dev);
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value = dm_gpio_get_value(&priv->cd_gpio);
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#endif
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/* if no CD return as 1 */
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if (value < 0)
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return 1;
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return value;
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}
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static int davinci_mmc_getwp(struct udevice *dev)
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{
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int value = -1;
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#if CONFIG_IS_ENABLED(DM_GPIO)
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struct davinci_mmc_priv *priv = dev_get_priv(dev);
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value = dm_gpio_get_value(&priv->wp_gpio);
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#endif
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/* if no WP return as 0 */
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if (value < 0)
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return 0;
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return value;
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}
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static const struct dm_mmc_ops davinci_mmc_ops = {
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.send_cmd = davinci_mmc_send_cmd,
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.set_ios = davinci_mmc_set_ios,
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.get_cd = davinci_mmc_getcd,
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.get_wp = davinci_mmc_getwp,
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};
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#endif
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#if !CONFIG_IS_ENABLED(DM_MMC)
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/* Called from board_mmc_init during startup. Can be called multiple times
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* depending on the number of slots available on board and controller
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*/
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int davinci_mmc_init(struct bd_info *bis, struct davinci_mmc *host)
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{
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host->cfg.name = "davinci";
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host->cfg.ops = &dmmc_ops;
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host->cfg.f_min = 200000;
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host->cfg.f_max = 25000000;
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host->cfg.voltages = host->voltages;
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host->cfg.host_caps = host->host_caps;
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host->cfg.b_max = DAVINCI_MAX_BLOCKS;
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mmc_create(&host->cfg, host);
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return 0;
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}
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#else
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static int davinci_mmc_probe(struct udevice *dev)
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{
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
|
struct davinci_mmc_plat *plat = dev_get_plat(dev);
|
|
struct davinci_mmc_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->reg_base = plat->reg_base;
|
|
priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID);
|
|
#if CONFIG_IS_ENABLED(DM_GPIO)
|
|
/* These GPIOs are optional */
|
|
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
|
|
gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
|
|
#endif
|
|
upriv->mmc = &plat->mmc;
|
|
|
|
return davinci_dm_mmc_init(dev);
|
|
}
|
|
|
|
static int davinci_mmc_bind(struct udevice *dev)
|
|
{
|
|
struct davinci_mmc_plat *plat = dev_get_plat(dev);
|
|
|
|
return mmc_bind(dev, &plat->mmc, &plat->cfg);
|
|
}
|
|
|
|
#if CONFIG_IS_ENABLED(OF_CONTROL)
|
|
static int davinci_mmc_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct davinci_mmc_plat *plat = dev_get_plat(dev);
|
|
struct mmc_config *cfg = &plat->cfg;
|
|
|
|
plat->reg_base = dev_read_addr_ptr(dev);
|
|
cfg->f_min = 200000;
|
|
cfg->f_max = 25000000;
|
|
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
|
|
cfg->host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
|
|
cfg->b_max = DAVINCI_MAX_BLOCKS;
|
|
cfg->name = "da830-mmc";
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id davinci_mmc_ids[] = {
|
|
{ .compatible = "ti,da830-mmc" },
|
|
{},
|
|
};
|
|
#endif
|
|
U_BOOT_DRIVER(ti_da830_mmc) = {
|
|
.name = "davinci_mmc",
|
|
.id = UCLASS_MMC,
|
|
#if CONFIG_IS_ENABLED(OF_CONTROL)
|
|
.of_match = davinci_mmc_ids,
|
|
.plat_auto = sizeof(struct davinci_mmc_plat),
|
|
.of_to_plat = davinci_mmc_of_to_plat,
|
|
#endif
|
|
#if CONFIG_BLK
|
|
.bind = davinci_mmc_bind,
|
|
#endif
|
|
.probe = davinci_mmc_probe,
|
|
.ops = &davinci_mmc_ops,
|
|
.priv_auto = sizeof(struct davinci_mmc_priv),
|
|
#if !CONFIG_IS_ENABLED(OF_CONTROL)
|
|
.flags = DM_FLAG_PRE_RELOC,
|
|
#endif
|
|
};
|
|
#endif
|