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9fea3696ef
The documentation for misc_read() says: Return: number of bytes read if OK (may be 0 if EOF), -ve on error The Rockchip efuse driver implements this so it should return the number of bytes read rather than zero on success. Fix this so that the driver follows the usual contract for read operations. Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
334 lines
7.6 KiB
C
334 lines
7.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <command.h>
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#include <display_options.h>
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#include <dm.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include <malloc.h>
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#include <misc.h>
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/* OTP Register Offsets */
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#define OTPC_SBPI_CTRL 0x0020
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#define OTPC_SBPI_CMD_VALID_PRE 0x0024
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#define OTPC_SBPI_CS_VALID_PRE 0x0028
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#define OTPC_SBPI_STATUS 0x002C
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#define OTPC_USER_CTRL 0x0100
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#define OTPC_USER_ADDR 0x0104
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#define OTPC_USER_ENABLE 0x0108
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#define OTPC_USER_QP 0x0120
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#define OTPC_USER_Q 0x0124
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#define OTPC_INT_STATUS 0x0304
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#define OTPC_SBPI_CMD0_OFFSET 0x1000
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#define OTPC_SBPI_CMD1_OFFSET 0x1004
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/* OTP Register bits and masks */
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#define OTPC_USER_ADDR_MASK GENMASK(31, 16)
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#define OTPC_USE_USER BIT(0)
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#define OTPC_USE_USER_MASK GENMASK(16, 16)
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#define OTPC_USER_FSM_ENABLE BIT(0)
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#define OTPC_USER_FSM_ENABLE_MASK GENMASK(16, 16)
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#define OTPC_SBPI_DONE BIT(1)
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#define OTPC_USER_DONE BIT(2)
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#define SBPI_DAP_ADDR 0x02
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#define SBPI_DAP_ADDR_SHIFT 8
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#define SBPI_DAP_ADDR_MASK GENMASK(31, 24)
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#define SBPI_CMD_VALID_MASK GENMASK(31, 16)
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#define SBPI_DAP_CMD_WRF 0xC0
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#define SBPI_DAP_REG_ECC 0x3A
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#define SBPI_ECC_ENABLE 0x00
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#define SBPI_ECC_DISABLE 0x09
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#define SBPI_ENABLE BIT(0)
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#define SBPI_ENABLE_MASK GENMASK(16, 16)
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#define OTPC_TIMEOUT 10000
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#define RK3588_OTPC_AUTO_CTRL 0x0004
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#define RK3588_ADDR_SHIFT 16
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#define RK3588_ADDR(n) ((n) << RK3588_ADDR_SHIFT)
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#define RK3588_BURST_SHIFT 8
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#define RK3588_BURST(n) ((n) << RK3588_BURST_SHIFT)
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#define RK3588_OTPC_AUTO_EN 0x0008
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#define RK3588_AUTO_EN BIT(0)
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#define RK3588_OTPC_DOUT0 0x0020
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#define RK3588_OTPC_INT_ST 0x0084
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#define RK3588_RD_DONE BIT(1)
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struct rockchip_otp_plat {
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void __iomem *base;
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};
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struct rockchip_otp_data {
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int (*read)(struct udevice *dev, int offset, void *buf, int size);
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int offset;
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int size;
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int block_size;
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};
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#if defined(DEBUG)
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static int dump_otp(struct cmd_tbl *cmdtp, int flag,
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int argc, char *const argv[])
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{
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struct udevice *dev;
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u8 data[4];
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int ret, i;
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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DM_DRIVER_GET(rockchip_otp), &dev);
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if (ret) {
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printf("%s: no misc-device found\n", __func__);
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return 0;
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}
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for (i = 0; true; i += sizeof(data)) {
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ret = misc_read(dev, i, &data, sizeof(data));
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if (ret <= 0)
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return 0;
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print_buffer(i, data, 1, sizeof(data), sizeof(data));
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}
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return 0;
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}
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U_BOOT_CMD(
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dump_otp, 1, 1, dump_otp,
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"Dump the content of the otp",
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""
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);
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#endif
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static int rockchip_otp_poll_timeout(struct rockchip_otp_plat *otp,
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u32 flag, u32 reg)
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{
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u32 status;
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int ret;
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ret = readl_poll_sleep_timeout(otp->base + reg, status,
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(status & flag), 1, OTPC_TIMEOUT);
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if (ret)
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return ret;
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/* Clear int flag */
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writel(flag, otp->base + reg);
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return 0;
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}
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static int rockchip_otp_ecc_enable(struct rockchip_otp_plat *otp, bool enable)
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{
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writel(SBPI_DAP_ADDR_MASK | (SBPI_DAP_ADDR << SBPI_DAP_ADDR_SHIFT),
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otp->base + OTPC_SBPI_CTRL);
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writel(SBPI_CMD_VALID_MASK | 0x1, otp->base + OTPC_SBPI_CMD_VALID_PRE);
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writel(SBPI_DAP_CMD_WRF | SBPI_DAP_REG_ECC,
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otp->base + OTPC_SBPI_CMD0_OFFSET);
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if (enable)
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writel(SBPI_ECC_ENABLE, otp->base + OTPC_SBPI_CMD1_OFFSET);
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else
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writel(SBPI_ECC_DISABLE, otp->base + OTPC_SBPI_CMD1_OFFSET);
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writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL);
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return rockchip_otp_poll_timeout(otp, OTPC_SBPI_DONE, OTPC_INT_STATUS);
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}
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static int rockchip_px30_otp_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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struct rockchip_otp_plat *otp = dev_get_plat(dev);
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u8 *buffer = buf;
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int ret;
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ret = rockchip_otp_ecc_enable(otp, false);
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if (ret)
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return ret;
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writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
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udelay(5);
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while (size--) {
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writel(offset++ | OTPC_USER_ADDR_MASK,
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otp->base + OTPC_USER_ADDR);
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writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
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otp->base + OTPC_USER_ENABLE);
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ret = rockchip_otp_poll_timeout(otp, OTPC_USER_DONE,
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OTPC_INT_STATUS);
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if (ret)
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goto read_end;
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*buffer++ = (u8)(readl(otp->base + OTPC_USER_Q) & 0xFF);
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}
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read_end:
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writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
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return ret;
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}
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static int rockchip_rk3568_otp_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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struct rockchip_otp_plat *otp = dev_get_plat(dev);
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u16 *buffer = buf;
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int ret;
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ret = rockchip_otp_ecc_enable(otp, false);
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if (ret)
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return ret;
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writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
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udelay(5);
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while (size--) {
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writel(offset++ | OTPC_USER_ADDR_MASK,
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otp->base + OTPC_USER_ADDR);
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writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
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otp->base + OTPC_USER_ENABLE);
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ret = rockchip_otp_poll_timeout(otp, OTPC_USER_DONE,
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OTPC_INT_STATUS);
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if (ret)
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goto read_end;
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*buffer++ = (u16)(readl(otp->base + OTPC_USER_Q) & 0xFFFF);
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}
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read_end:
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writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
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return ret;
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}
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static int rockchip_rk3588_otp_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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struct rockchip_otp_plat *otp = dev_get_plat(dev);
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u32 *buffer = buf;
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int ret;
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while (size--) {
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writel(RK3588_ADDR(offset++) | RK3588_BURST(1),
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otp->base + RK3588_OTPC_AUTO_CTRL);
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writel(RK3588_AUTO_EN, otp->base + RK3588_OTPC_AUTO_EN);
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ret = rockchip_otp_poll_timeout(otp, RK3588_RD_DONE,
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RK3588_OTPC_INT_ST);
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if (ret)
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return ret;
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*buffer++ = readl(otp->base + RK3588_OTPC_DOUT0);
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}
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return 0;
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}
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static int rockchip_otp_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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const struct rockchip_otp_data *data =
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(void *)dev_get_driver_data(dev);
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u32 block_start, block_end, block_offset, blocks;
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u8 *buffer;
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int ret;
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if (offset < 0 || !buf || size <= 0 || offset + size > data->size)
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return -EINVAL;
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if (!data->read)
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return -ENOSYS;
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offset += data->offset;
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if (data->block_size <= 1) {
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ret = data->read(dev, offset, buf, size);
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goto done;
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}
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block_start = offset / data->block_size;
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block_offset = offset % data->block_size;
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block_end = DIV_ROUND_UP(offset + size, data->block_size);
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blocks = block_end - block_start;
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buffer = calloc(blocks, data->block_size);
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if (!buffer)
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return -ENOMEM;
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ret = data->read(dev, block_start, buffer, blocks);
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if (!ret)
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memcpy(buf, buffer + block_offset, size);
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free(buffer);
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done:
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return ret < 0 ? ret : size;
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}
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static const struct misc_ops rockchip_otp_ops = {
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.read = rockchip_otp_read,
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};
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static int rockchip_otp_of_to_plat(struct udevice *dev)
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{
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struct rockchip_otp_plat *plat = dev_get_plat(dev);
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plat->base = dev_read_addr_ptr(dev);
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return 0;
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}
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static const struct rockchip_otp_data px30_data = {
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.read = rockchip_px30_otp_read,
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.size = 0x40,
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};
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static const struct rockchip_otp_data rk3568_data = {
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.read = rockchip_rk3568_otp_read,
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.size = 0x80,
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.block_size = 2,
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};
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static const struct rockchip_otp_data rk3588_data = {
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.read = rockchip_rk3588_otp_read,
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.offset = 0xC00,
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.size = 0x400,
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.block_size = 4,
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};
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static const struct udevice_id rockchip_otp_ids[] = {
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{
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.compatible = "rockchip,px30-otp",
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.data = (ulong)&px30_data,
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},
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{
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.compatible = "rockchip,rk3308-otp",
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.data = (ulong)&px30_data,
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},
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{
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.compatible = "rockchip,rk3568-otp",
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.data = (ulong)&rk3568_data,
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},
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{
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.compatible = "rockchip,rk3588-otp",
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.data = (ulong)&rk3588_data,
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},
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{}
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};
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U_BOOT_DRIVER(rockchip_otp) = {
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.name = "rockchip_otp",
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.id = UCLASS_MISC,
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.of_match = rockchip_otp_ids,
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.of_to_plat = rockchip_otp_of_to_plat,
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.plat_auto = sizeof(struct rockchip_otp_plat),
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.ops = &rockchip_otp_ops,
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};
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