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7eace38d54
If the clock driver does not offer a clk_enable ops, then the system will
return -ENOSYS.
The clk_enable works with CCF (common clock framework).
Some clocks in some cases (like the generic clock for some products: sama5d2)
do not have the clk_enable primitive, and in this case probing of the driver
will fail.
This patch changes the behavior to return an error in case there is really
an error, and not a missing primitive.
If the clock driver does not have an enable primitive, most likely clocks
are always enabled or enabled in the set_rate primitives.
Fixes: 81f16438d4 ("mmc: atmel-sdhci: enable the required generic clock")
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
137 lines
2.9 KiB
C
137 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Atmel Corporation
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* Wenyou.Yang <wenyou.yang@atmel.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <malloc.h>
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#include <sdhci.h>
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#include <asm/arch/clk.h>
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#define ATMEL_SDHC_MIN_FREQ 400000
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#define ATMEL_SDHC_GCK_RATE 240000000
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#ifndef CONFIG_DM_MMC
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int atmel_sdhci_init(void *regbase, u32 id)
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{
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struct sdhci_host *host;
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u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ;
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host = (struct sdhci_host *)calloc(1, sizeof(struct sdhci_host));
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if (!host) {
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printf("%s: sdhci_host calloc failed\n", __func__);
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return -ENOMEM;
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}
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host->name = "atmel_sdhci";
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host->ioaddr = regbase;
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host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
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max_clk = at91_get_periph_generated_clk(id);
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if (!max_clk) {
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printf("%s: Failed to get the proper clock\n", __func__);
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free(host);
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return -ENODEV;
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}
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host->max_clk = max_clk;
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add_sdhci(host, 0, min_clk);
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return 0;
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}
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#else
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DECLARE_GLOBAL_DATA_PTR;
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struct atmel_sdhci_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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static int atmel_sdhci_probe(struct udevice *dev)
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{
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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u32 max_clk;
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struct clk clk;
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int ret;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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ret = clk_enable(&clk);
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if (ret)
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return ret;
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host->name = dev->name;
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host->ioaddr = dev_read_addr_ptr(dev);
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host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
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host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"bus-width", 4);
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ret = clk_get_by_index(dev, 1, &clk);
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if (ret)
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return ret;
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clk_set_rate(&clk, ATMEL_SDHC_GCK_RATE);
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max_clk = clk_get_rate(&clk);
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if (!max_clk)
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return -EINVAL;
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ret = clk_enable(&clk);
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/* return error only if the clock really has a clock enable func */
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if (ret && ret != -ENOSYS)
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return ret;
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ret = mmc_of_parse(dev, &plat->cfg);
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if (ret)
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return ret;
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host->max_clk = max_clk;
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host->mmc = &plat->mmc;
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host->mmc->dev = dev;
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ret = sdhci_setup_cfg(&plat->cfg, host, 0, ATMEL_SDHC_MIN_FREQ);
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if (ret)
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return ret;
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host->mmc->priv = host;
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upriv->mmc = host->mmc;
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clk_free(&clk);
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return sdhci_probe(dev);
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}
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static int atmel_sdhci_bind(struct udevice *dev)
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{
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struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id atmel_sdhci_ids[] = {
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{ .compatible = "atmel,sama5d2-sdhci" },
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{ .compatible = "microchip,sam9x60-sdhci" },
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{ .compatible = "microchip,sama7g5-sdhci" },
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{ }
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};
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U_BOOT_DRIVER(atmel_sdhci_drv) = {
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.name = "atmel_sdhci",
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.id = UCLASS_MMC,
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.of_match = atmel_sdhci_ids,
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.ops = &sdhci_ops,
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.bind = atmel_sdhci_bind,
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.probe = atmel_sdhci_probe,
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.priv_auto_alloc_size = sizeof(struct sdhci_host),
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.platdata_auto_alloc_size = sizeof(struct atmel_sdhci_plat),
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};
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#endif
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