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https://github.com/AsahiLinux/u-boot
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f76750d111
This converts the following to Kconfig: CONFIG_CONS_INDEX CONFIG_DEBUG_UART_CLOCK CONFIG_FSL_TZPC_BP147 CONFIG_GENERIC_ATMEL_MCI CONFIG_IDENT_STRING CONFIG_LIBATA CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE CONFIG_LPC32XX_GPIO CONFIG_MP CONFIG_MPC8XXX_GPIO CONFIG_MTD_PARTITIONS CONFIG_MVGBE CONFIG_MXC_GPIO CONFIG_NR_DRAM_BANKS CONFIG_OF_BOARD_SETUP CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_OF_SYSTEM_SETUP CONFIG_PREBOOT CONFIG_ROCKCHIP_SERIAL CONFIG_RTC_ENABLE_32KHZ_OUTPUT CONFIG_RTC_MV CONFIG_SCSI_AHCI CONFIG_SF_DEFAULT_BUS CONFIG_SF_DEFAULT_CS CONFIG_SF_DEFAULT_SPEED CONFIG_SOFT_SPI CONFIG_SPI_FLASH_EON CONFIG_SPI_FLASH_MACRONIX CONFIG_SPI_FLASH_MTD CONFIG_SPI_FLASH_SPANSION CONFIG_SPI_FLASH_SST CONFIG_SPI_FLASH_STMICRO CONFIG_SUPPORT_RAW_INITRD CONFIG_SYS_ARCH_TIMER CONFIG_SYS_BOARD CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE CONFIG_SYS_DCACHE_OFF CONFIG_SYS_FDT_SAVE_ADDRESS CONFIG_SYS_FLASH_CFI CONFIG_SYS_FSL_ERRATUM_ESDHC135 CONFIG_SYS_HAS_SERDES CONFIG_SYS_L2CACHE_OFF CONFIG_SYS_LITTLE_ENDIAN CONFIG_SYS_LOAD_ADDR CONFIG_SYS_MMCSD_FS_BOOT_PARTITION CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR CONFIG_SYS_NS16550 CONFIG_SYS_PLLFIN CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_TIMER_SYS_TICK_CH CONFIG_USB_EHCI_FSL CONFIG_U_QE CONFIG_VERSION_VARIABLE Signed-off-by: Tom Rini <trini@konsulko.com>
80 lines
2 KiB
C
80 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010-2012
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#ifndef _TEGRA_COMMON_H_
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#define _TEGRA_COMMON_H_
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#include <linux/sizes.h>
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#include <linux/stringify.h>
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/*
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* High Level Configuration Options
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*/
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#include <asm/arch/tegra.h> /* get chip and board defs */
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/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
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#ifndef CONFIG_ARM64
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#define CONFIG_SYS_TIMER_RATE 1000000
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#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
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#endif
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/* Environment */
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/*
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* NS16550 Configuration
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*/
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#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
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/*
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* Common HW configuration.
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* If this varies between SoCs later, move to tegraNN-common.h
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* Note: This is number of devices, not max device ID.
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*/
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#define CONFIG_SYS_MMC_MAX_DEVICE 4
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/*
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* Increasing the size of the IO buffer as default nfsargs size is more
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* than 256 and so it is not possible to edit it
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*/
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#define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
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#ifdef CONFIG_ARM64
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#define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb"
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#else
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#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb"
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#endif
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
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#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
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#ifndef CONFIG_ARM64
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
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#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#endif
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#ifndef CONFIG_ARM64
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/* Defines for SPL */
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#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \
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CONFIG_SPL_TEXT_BASE)
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
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#endif
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#endif /* _TEGRA_COMMON_H_ */
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