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https://github.com/AsahiLinux/u-boot
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66ef85da61
ZynqMP mini configurations works without PMU firmware that's why there is no reason to enable the driver and check if it was probed properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
698 lines
13 KiB
C
698 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <env.h>
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#include <init.h>
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#include <sata.h>
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#include <ahci.h>
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#include <scsi.h>
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#include <malloc.h>
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#include <wdt.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/psu_init_gpl.h>
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#include <asm/io.h>
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#include <dm/device.h>
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#include <dm/uclass.h>
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#include <usb.h>
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#include <dwc3-uboot.h>
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#include <zynqmppl.h>
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#include <zynqmp_firmware.h>
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#include <g_dnl.h>
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#include <linux/sizes.h>
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#include "pm_cfg_obj.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
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!defined(CONFIG_SPL_BUILD)
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static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
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static const struct {
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u32 id;
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u32 ver;
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char *name;
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bool evexists;
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} zynqmp_devices[] = {
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{
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.id = 0x10,
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.name = "3eg",
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},
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{
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.id = 0x10,
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.ver = 0x2c,
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.name = "3cg",
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},
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{
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.id = 0x11,
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.name = "2eg",
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},
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{
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.id = 0x11,
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.ver = 0x2c,
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.name = "2cg",
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},
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{
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.id = 0x20,
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.name = "5ev",
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.evexists = 1,
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},
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{
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.id = 0x20,
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.ver = 0x100,
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.name = "5eg",
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.evexists = 1,
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},
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{
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.id = 0x20,
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.ver = 0x12c,
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.name = "5cg",
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.evexists = 1,
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},
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{
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.id = 0x21,
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.name = "4ev",
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.evexists = 1,
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},
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{
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.id = 0x21,
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.ver = 0x100,
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.name = "4eg",
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.evexists = 1,
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},
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{
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.id = 0x21,
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.ver = 0x12c,
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.name = "4cg",
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.evexists = 1,
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},
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{
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.id = 0x30,
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.name = "7ev",
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.evexists = 1,
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},
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{
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.id = 0x30,
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.ver = 0x100,
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.name = "7eg",
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.evexists = 1,
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},
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{
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.id = 0x30,
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.ver = 0x12c,
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.name = "7cg",
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.evexists = 1,
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},
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{
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.id = 0x38,
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.name = "9eg",
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},
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{
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.id = 0x38,
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.ver = 0x2c,
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.name = "9cg",
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},
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{
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.id = 0x39,
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.name = "6eg",
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},
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{
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.id = 0x39,
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.ver = 0x2c,
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.name = "6cg",
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},
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{
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.id = 0x40,
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.name = "11eg",
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},
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{ /* For testing purpose only */
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.id = 0x50,
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.ver = 0x2c,
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.name = "15cg",
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},
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{
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.id = 0x50,
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.name = "15eg",
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},
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{
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.id = 0x58,
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.name = "19eg",
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},
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{
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.id = 0x59,
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.name = "17eg",
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},
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{
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.id = 0x61,
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.name = "21dr",
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},
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{
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.id = 0x63,
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.name = "23dr",
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},
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{
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.id = 0x65,
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.name = "25dr",
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},
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{
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.id = 0x64,
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.name = "27dr",
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},
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{
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.id = 0x60,
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.name = "28dr",
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},
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{
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.id = 0x62,
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.name = "29dr",
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},
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{
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.id = 0x66,
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.name = "39dr",
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},
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{
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.id = 0x7b,
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.name = "48dr",
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},
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{
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.id = 0x7e,
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.name = "49dr",
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},
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};
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#endif
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int chip_id(unsigned char id)
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{
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struct pt_regs regs;
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int val = -EINVAL;
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if (current_el() != 3) {
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regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
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regs.regs[1] = 0;
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regs.regs[2] = 0;
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regs.regs[3] = 0;
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smc_call(®s);
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/*
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* SMC returns:
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* regs[0][31:0] = status of the operation
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* regs[0][63:32] = CSU.IDCODE register
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* regs[1][31:0] = CSU.version register
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* regs[1][63:32] = CSU.IDCODE2 register
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*/
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switch (id) {
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case IDCODE:
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regs.regs[0] = upper_32_bits(regs.regs[0]);
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regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
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ZYNQMP_CSU_IDCODE_SVD_MASK;
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regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
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val = regs.regs[0];
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break;
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case VERSION:
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regs.regs[1] = lower_32_bits(regs.regs[1]);
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regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
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val = regs.regs[1];
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break;
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case IDCODE2:
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regs.regs[1] = lower_32_bits(regs.regs[1]);
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regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
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val = regs.regs[1];
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break;
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default:
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printf("%s, Invalid Req:0x%x\n", __func__, id);
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}
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} else {
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switch (id) {
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case IDCODE:
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val = readl(ZYNQMP_CSU_IDCODE_ADDR);
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val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
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ZYNQMP_CSU_IDCODE_SVD_MASK;
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val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
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break;
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case VERSION:
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val = readl(ZYNQMP_CSU_VER_ADDR);
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val &= ZYNQMP_CSU_SILICON_VER_MASK;
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break;
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default:
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printf("%s, Invalid Req:0x%x\n", __func__, id);
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}
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}
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return val;
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}
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#define ZYNQMP_VERSION_SIZE 9
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#define ZYNQMP_PL_STATUS_BIT 9
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#define ZYNQMP_IPDIS_VCU_BIT 8
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#define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
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#define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
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#define ZYNQMP_CSU_VCUDIS_VER_MASK ZYNQMP_CSU_VERSION_MASK & \
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~BIT(ZYNQMP_IPDIS_VCU_BIT)
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#define MAX_VARIANTS_EV 3
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#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
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!defined(CONFIG_SPL_BUILD)
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static char *zynqmp_get_silicon_idcode_name(void)
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{
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u32 i, id, ver, j;
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char *buf;
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static char name[ZYNQMP_VERSION_SIZE];
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id = chip_id(IDCODE);
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ver = chip_id(IDCODE2);
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for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
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if (zynqmp_devices[i].id == id) {
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if (zynqmp_devices[i].evexists &&
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!(ver & ZYNQMP_PL_STATUS_MASK))
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break;
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if (zynqmp_devices[i].ver == (ver &
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ZYNQMP_CSU_VERSION_MASK))
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break;
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}
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}
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if (i >= ARRAY_SIZE(zynqmp_devices))
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return "unknown";
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strncat(name, "zu", 2);
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if (!zynqmp_devices[i].evexists ||
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(ver & ZYNQMP_PL_STATUS_MASK)) {
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strncat(name, zynqmp_devices[i].name,
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ZYNQMP_VERSION_SIZE - 3);
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return name;
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}
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/*
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* Here we are means, PL not powered up and ev variant
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* exists. So, we need to ignore VCU disable bit(8) in
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* version and findout if its CG or EG/EV variant.
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*/
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for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
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if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
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(ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
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strncat(name, zynqmp_devices[i].name,
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ZYNQMP_VERSION_SIZE - 3);
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break;
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}
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}
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if (j >= MAX_VARIANTS_EV)
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return "unknown";
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if (strstr(name, "eg") || strstr(name, "ev")) {
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buf = strstr(name, "e");
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*buf = '\0';
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}
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return name;
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}
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#endif
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int board_early_init_f(void)
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{
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int ret = 0;
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#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
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ret = psu_init();
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#endif
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return ret;
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}
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static int multi_boot(void)
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{
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u32 multiboot;
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multiboot = readl(&csu_base->multi_boot);
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printf("Multiboot:\t%x\n", multiboot);
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return 0;
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}
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int board_init(void)
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{
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#if defined(CONFIG_ZYNQMP_FIRMWARE)
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struct udevice *dev;
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uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
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if (!dev)
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panic("PMU Firmware device not found - Enable it");
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#endif
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#if defined(CONFIG_SPL_BUILD)
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/* Check *at build time* if the filename is an non-empty string */
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if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
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zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
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zynqmp_pm_cfg_obj_size);
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#endif
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printf("EL Level:\tEL%d\n", current_el());
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#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
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!defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
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defined(CONFIG_SPL_BUILD))
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if (current_el() != 3) {
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zynqmppl.name = zynqmp_get_silicon_idcode_name();
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printf("Chip ID:\t%s\n", zynqmppl.name);
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fpga_init();
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fpga_add(fpga_xilinx, &zynqmppl);
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}
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#endif
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if (current_el() == 3)
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multi_boot();
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return 0;
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}
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int board_early_init_r(void)
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{
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u32 val;
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if (current_el() != 3)
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return 0;
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val = readl(&crlapb_base->timestamp_ref_ctrl);
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val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
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if (!val) {
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val = readl(&crlapb_base->timestamp_ref_ctrl);
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val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
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writel(val, &crlapb_base->timestamp_ref_ctrl);
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/* Program freq register in System counter */
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writel(zynqmp_get_system_timer_freq(),
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&iou_scntr_secure->base_frequency_id_register);
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/* And enable system counter */
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writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
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&iou_scntr_secure->counter_control_register);
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}
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return 0;
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}
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unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
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char * const argv[])
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{
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int ret = 0;
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if (current_el() > 1) {
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smp_kick_all_cpus();
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dcache_disable();
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armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
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ES_TO_AARCH64);
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} else {
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printf("FAIL: current EL is not above EL1\n");
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ret = EINVAL;
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}
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return ret;
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}
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#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
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int dram_init_banksize(void)
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{
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int ret;
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ret = fdtdec_setup_memory_banksize();
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if (ret)
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return ret;
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mem_map_fill();
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return 0;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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#else
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int dram_init_banksize(void)
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{
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#if defined(CONFIG_NR_DRAM_BANKS)
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = get_effective_memsize();
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#endif
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mem_map_fill();
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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#endif
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void reset_cpu(ulong addr)
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{
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}
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#if defined(CONFIG_BOARD_LATE_INIT)
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static const struct {
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u32 bit;
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const char *name;
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} reset_reasons[] = {
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{ RESET_REASON_DEBUG_SYS, "DEBUG" },
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{ RESET_REASON_SOFT, "SOFT" },
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{ RESET_REASON_SRST, "SRST" },
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{ RESET_REASON_PSONLY, "PS-ONLY" },
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{ RESET_REASON_PMU, "PMU" },
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{ RESET_REASON_INTERNAL, "INTERNAL" },
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{ RESET_REASON_EXTERNAL, "EXTERNAL" },
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{}
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};
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static int reset_reason(void)
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{
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u32 reg;
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int i, ret;
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const char *reason = NULL;
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ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, ®);
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if (ret)
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return -EINVAL;
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puts("Reset reason:\t");
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for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
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if (reg & reset_reasons[i].bit) {
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reason = reset_reasons[i].name;
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printf("%s ", reset_reasons[i].name);
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break;
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}
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}
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puts("\n");
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env_set("reset_reason", reason);
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ret = zynqmp_mmio_write(~0, ~0, (ulong)&crlapb_base->reset_reason);
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if (ret)
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return -EINVAL;
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return ret;
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}
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static int set_fdtfile(void)
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{
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char *compatible, *fdtfile;
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const char *suffix = ".dtb";
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const char *vendor = "xilinx/";
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if (env_get("fdtfile"))
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return 0;
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compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
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if (compatible) {
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debug("Compatible: %s\n", compatible);
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/* Discard vendor prefix */
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strsep(&compatible, ",");
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fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
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strlen(suffix) + 1);
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if (!fdtfile)
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return -ENOMEM;
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sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
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env_set("fdtfile", fdtfile);
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free(fdtfile);
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}
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return 0;
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}
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int board_late_init(void)
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{
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u32 reg = 0;
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|
u8 bootmode;
|
|
struct udevice *dev;
|
|
int bootseq = -1;
|
|
int bootseq_len = 0;
|
|
int env_targets_len = 0;
|
|
const char *mode;
|
|
char *new_targets;
|
|
char *env_targets;
|
|
int ret;
|
|
ulong initrd_hi;
|
|
|
|
#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
|
|
usb_ether_init();
|
|
#endif
|
|
|
|
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
|
|
debug("Saved variables - Skipping\n");
|
|
return 0;
|
|
}
|
|
|
|
ret = set_fdtfile();
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
|
|
if (ret)
|
|
return -EINVAL;
|
|
|
|
if (reg >> BOOT_MODE_ALT_SHIFT)
|
|
reg >>= BOOT_MODE_ALT_SHIFT;
|
|
|
|
bootmode = reg & BOOT_MODES_MASK;
|
|
|
|
puts("Bootmode: ");
|
|
switch (bootmode) {
|
|
case USB_MODE:
|
|
puts("USB_MODE\n");
|
|
mode = "usb";
|
|
env_set("modeboot", "usb_dfu_spl");
|
|
break;
|
|
case JTAG_MODE:
|
|
puts("JTAG_MODE\n");
|
|
mode = "jtag pxe dhcp";
|
|
env_set("modeboot", "jtagboot");
|
|
break;
|
|
case QSPI_MODE_24BIT:
|
|
case QSPI_MODE_32BIT:
|
|
mode = "qspi0";
|
|
puts("QSPI_MODE\n");
|
|
env_set("modeboot", "qspiboot");
|
|
break;
|
|
case EMMC_MODE:
|
|
puts("EMMC_MODE\n");
|
|
if (uclass_get_device_by_name(UCLASS_MMC,
|
|
"mmc@ff160000", &dev) &&
|
|
uclass_get_device_by_name(UCLASS_MMC,
|
|
"sdhci@ff160000", &dev)) {
|
|
puts("Boot from EMMC but without SD0 enabled!\n");
|
|
return -1;
|
|
}
|
|
debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
|
|
|
|
mode = "mmc";
|
|
bootseq = dev->seq;
|
|
break;
|
|
case SD_MODE:
|
|
puts("SD_MODE\n");
|
|
if (uclass_get_device_by_name(UCLASS_MMC,
|
|
"mmc@ff160000", &dev) &&
|
|
uclass_get_device_by_name(UCLASS_MMC,
|
|
"sdhci@ff160000", &dev)) {
|
|
puts("Boot from SD0 but without SD0 enabled!\n");
|
|
return -1;
|
|
}
|
|
debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
|
|
|
|
mode = "mmc";
|
|
bootseq = dev->seq;
|
|
env_set("modeboot", "sdboot");
|
|
break;
|
|
case SD1_LSHFT_MODE:
|
|
puts("LVL_SHFT_");
|
|
/* fall through */
|
|
case SD_MODE1:
|
|
puts("SD_MODE1\n");
|
|
if (uclass_get_device_by_name(UCLASS_MMC,
|
|
"mmc@ff170000", &dev) &&
|
|
uclass_get_device_by_name(UCLASS_MMC,
|
|
"sdhci@ff170000", &dev)) {
|
|
puts("Boot from SD1 but without SD1 enabled!\n");
|
|
return -1;
|
|
}
|
|
debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
|
|
|
|
mode = "mmc";
|
|
bootseq = dev->seq;
|
|
env_set("modeboot", "sdboot");
|
|
break;
|
|
case NAND_MODE:
|
|
puts("NAND_MODE\n");
|
|
mode = "nand0";
|
|
env_set("modeboot", "nandboot");
|
|
break;
|
|
default:
|
|
mode = "";
|
|
printf("Invalid Boot Mode:0x%x\n", bootmode);
|
|
break;
|
|
}
|
|
|
|
if (bootseq >= 0) {
|
|
bootseq_len = snprintf(NULL, 0, "%i", bootseq);
|
|
debug("Bootseq len: %x\n", bootseq_len);
|
|
}
|
|
|
|
/*
|
|
* One terminating char + one byte for space between mode
|
|
* and default boot_targets
|
|
*/
|
|
env_targets = env_get("boot_targets");
|
|
if (env_targets)
|
|
env_targets_len = strlen(env_targets);
|
|
|
|
new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
|
|
bootseq_len);
|
|
if (!new_targets)
|
|
return -ENOMEM;
|
|
|
|
if (bootseq >= 0)
|
|
sprintf(new_targets, "%s%x %s", mode, bootseq,
|
|
env_targets ? env_targets : "");
|
|
else
|
|
sprintf(new_targets, "%s %s", mode,
|
|
env_targets ? env_targets : "");
|
|
|
|
env_set("boot_targets", new_targets);
|
|
|
|
initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
|
|
initrd_hi = round_down(initrd_hi, SZ_16M);
|
|
env_set_addr("initrd_high", (void *)initrd_hi);
|
|
|
|
env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
|
|
|
|
reset_reason();
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int checkboard(void)
|
|
{
|
|
puts("Board: Xilinx ZynqMP\n");
|
|
return 0;
|
|
}
|