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https://github.com/AsahiLinux/u-boot
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9df16c5937
Add helper code for PVR (Processor Version Register) data handling. It will be used by the UCLASS_CPU driver to populate cpuinfo fields at runtime. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-13-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
120 lines
3.5 KiB
Text
120 lines
3.5 KiB
Text
if TARGET_MICROBLAZE_GENERIC
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config SYS_BOARD
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default "microblaze-generic"
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config SYS_VENDOR
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default "xilinx"
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config SYS_CONFIG_NAME
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string "Board configuration name"
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default "microblaze-generic"
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help
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This option contains information about board configuration name.
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Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
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will be used for board configuration.
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config XILINX_MICROBLAZE0_USE_MSR_INSTR
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int "USE_MSR_INSTR range (0:1)"
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default 0
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config XILINX_MICROBLAZE0_USE_PCMP_INSTR
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int "USE_PCMP_INSTR range (0:1)"
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default 0
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config XILINX_MICROBLAZE0_USE_BARREL
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int "USE_BARREL range (0:1)"
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default 0
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config XILINX_MICROBLAZE0_USE_DIV
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int "USE_DIV range (0:1)"
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default 0
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config XILINX_MICROBLAZE0_USE_HW_MUL
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int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
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default 0
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config XILINX_MICROBLAZE0_HW_VER
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string "Core version number"
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default "7.10.d"
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config XILINX_MICROBLAZE0_FPGA_FAMILY
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string "Targeted FPGA family"
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default "virtex5"
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help
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This option contains info about the target FPGA architecture
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(Zynq-7000, UltraScale+ Kintex, etc) that the MicroBlaze soft core is
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implemented on. It corresponds to the C_FAMILY hdl parameter.
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config XILINX_MICROBLAZE0_USR_EXCEP
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bool "MicroBlaze user exception support"
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default y
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help
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Enable this option in order to install the user exception handler
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(_exception_handler routine from arch/microblaze/cpu/exception.c) in
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the exception vector table. The user exception vector is located at
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C_BASE_VECTORS + 0x8 address.
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config XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP
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bool "MicroBlaze delay slot exception support"
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default y
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help
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Enable this option if the MicroBlaze processor supports exceptions
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caused by delay slot instructions (processor version >= v5.00). When
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enabled, the hw exception handler will print a message indicating
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whether the exception was triggered by a delay slot instruction.
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config XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
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hex "Location of MicroBlaze vectors"
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default 0x0
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help
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Memory address location of the exception vector table. It is
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configurable via the C_BASE_VECTORS hdl parameter.
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config XILINX_MICROBLAZE0_USE_WDC
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bool "MicroBlaze wdc instruction support"
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default y
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help
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Enable this option if the MicroBlaze processor is configured with
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support for the "wdc" (Write to Data Cache) instruction.
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config SPL_XILINX_MICROBLAZE0_USE_WDC
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bool
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default XILINX_MICROBLAZE0_USE_WDC
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config XILINX_MICROBLAZE0_USE_WIC
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bool "MicroBlaze wic instruction support"
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default y
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help
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Enable this option if the MicroBlaze processor is configured with
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support for the "wic" (Write to Instruction Cache) instruction.
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config SPL_XILINX_MICROBLAZE0_USE_WIC
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bool
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default XILINX_MICROBLAZE0_USE_WIC
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config XILINX_MICROBLAZE0_DCACHE_SIZE
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int "Default data cache size"
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default 32768
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help
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This fallback size will be used when no dcache info can be found in
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the device tree, or when the data cache is flushed very early in the
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boot process, before device tree is available.
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config XILINX_MICROBLAZE0_ICACHE_SIZE
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int "Default instruction cache size"
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default 32768
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help
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This fallback size will be used when no icache info can be found in
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the device tree, or when the instruction cache is flushed very early
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in the boot process, before device tree is available.
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config XILINX_MICROBLAZE0_PVR
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bool "MicroBlaze PVR support"
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help
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Enables helper functions and macros needed to manipulate PVR
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(Processor Version Register) data. Currently, only the microblaze
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UCLASS_CPU driver makes use of this feature to retrieve CPU info at
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runtime.
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endif
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