mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-25 12:33:41 +00:00
552a848e4f
Change is consistent with other SOCs and it is in preparation for adding SOMs. SOC's related files are moved from cpu/ to mach-imx/<SOC>. This change is also coherent with the structure in kernel. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Akshay Bhat <akshaybhat@timesys.com> CC: Ken Lin <Ken.Lin@advantech.com.tw> CC: Marek Vasut <marek.vasut@gmail.com> CC: Heiko Schocher <hs@denx.de> CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com> CC: Christian Gmeiner <christian.gmeiner@gmail.com> CC: Stefan Roese <sr@denx.de> CC: Patrick Bruenn <p.bruenn@beckhoff.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Nikita Kiryanov <nikita@compulab.co.il> CC: Otavio Salvador <otavio@ossystems.com.br> CC: "Eric Bénard" <eric@eukrea.com> CC: Jagan Teki <jagan@amarulasolutions.com> CC: Ye Li <ye.li@nxp.com> CC: Peng Fan <peng.fan@nxp.com> CC: Adrian Alonso <adrian.alonso@nxp.com> CC: Alison Wang <b18965@freescale.com> CC: Tim Harvey <tharvey@gateworks.com> CC: Martin Donnelly <martin.donnelly@ge.com> CC: Marcin Niestroj <m.niestroj@grinn-global.com> CC: Lukasz Majewski <lukma@denx.de> CC: Adam Ford <aford173@gmail.com> CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr> CC: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Soeren Moch <smoch@web.de> CC: Richard Hu <richard.hu@technexion.com> CC: Wig Cheng <wig.cheng@technexion.com> CC: Vanessa Maegima <vanessa.maegima@nxp.com> CC: Max Krummenacher <max.krummenacher@toradex.com> CC: Stefan Agner <stefan.agner@toradex.com> CC: Markus Niebel <Markus.Niebel@tq-group.com> CC: Breno Lima <breno.lima@nxp.com> CC: Francesco Montefoschi <francesco.montefoschi@udoo.org> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Scott Wood <oss@buserror.net> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Anatolij Gustschin <agust@denx.de> CC: Simon Glass <sjg@chromium.org> CC: "Andrew F. Davis" <afd@ti.com> CC: "Łukasz Majewski" <l.majewski@samsung.com> CC: Patrice Chotard <patrice.chotard@st.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Hans de Goede <hdegoede@redhat.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stephen Warren <swarren@nvidia.com> CC: Andre Przywara <andre.przywara@arm.com> CC: "Álvaro Fernández Rojas" <noltari@gmail.com> CC: York Sun <york.sun@nxp.com> CC: Xiaoliang Yang <xiaoliang.yang@nxp.com> CC: Chen-Yu Tsai <wens@csie.org> CC: George McCollister <george.mccollister@gmail.com> CC: Sven Ebenfeld <sven.ebenfeld@gmail.com> CC: Filip Brozovic <fbrozovic@gmail.com> CC: Petr Kulhavy <brain@jikos.cz> CC: Eric Nelson <eric@nelint.com> CC: Bai Ping <ping.bai@nxp.com> CC: Anson Huang <Anson.Huang@nxp.com> CC: Sanchayan Maity <maitysanchayan@gmail.com> CC: Lokesh Vutla <lokeshvutla@ti.com> CC: Patrick Delaunay <patrick.delaunay@st.com> CC: Gary Bisson <gary.bisson@boundarydevices.com> CC: Alexander Graf <agraf@suse.de> CC: u-boot@lists.denx.de Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
517 lines
12 KiB
C
517 lines
12 KiB
C
/*
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* Copyright (C) 2016 samtec automotive software & electronics gmbh
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*
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* Author: Christoph Fritz <chf.fritz@googlemail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/io.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <linux/sizes.h>
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <mmc.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <power/pmic.h>
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#include <power/pfuze100_pmic.h>
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#include <usb.h>
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#include <usb/ehci-ci.h>
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#include <pwm.h>
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#include <wait_bit.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
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PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \
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PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
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PAD_CTL_SRE_FAST)
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#define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm
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#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \
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PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \
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PAD_CTL_SRE_FAST)
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#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
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PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm)
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#define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
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#define USDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
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PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST)
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#define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
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PAD_CTL_PKE)
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
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MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_LCD1_VSYNC__GPIO3_IO_28 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc4_pads[] = {
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MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
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MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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static iomux_v3_cfg_t const fec1_pads[] = {
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MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) |
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MUX_MODE_SION,
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/* LAN8720 PHY Reset */
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MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const pwm_led_pads[] = {
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MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
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MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
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MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
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};
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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#define PHY_RESET IMX_GPIO_NR(5, 9)
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int board_eth_init(bd_t *bis)
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{
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struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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int ret;
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unsigned char eth1addr[6];
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/* just to get secound mac address */
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imx_get_mac_from_fuse(1, eth1addr);
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if (!getenv("eth1addr") && is_valid_ethaddr(eth1addr))
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eth_setenv_enetaddr("eth1addr", eth1addr);
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imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
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/*
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* Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
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* ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
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* ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
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*/
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clrsetbits_le32(&iomuxc_regs->gpr[1],
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IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
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IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
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IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
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IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
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ret = enable_fec_anatop_clock(0, ENET_50MHZ);
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if (ret)
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goto eth_fail;
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/* reset phy */
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gpio_direction_output(PHY_RESET, 0);
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mdelay(16);
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gpio_set_value(PHY_RESET, 1);
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mdelay(1);
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ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
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IMX_FEC_BASE);
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if (ret)
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goto eth_fail;
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return ret;
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eth_fail:
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printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
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gpio_set_value(PHY_RESET, 0);
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return ret;
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}
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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/* I2C1 for PMIC */
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static struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
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.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
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.gp = IMX_GPIO_NR(1, 0),
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},
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.sda = {
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.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
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.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
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.gp = IMX_GPIO_NR(1, 1),
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},
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};
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static struct pmic *pfuze_init(unsigned char i2cbus)
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{
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struct pmic *p;
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int ret;
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u32 reg;
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ret = power_pfuze100_init(i2cbus);
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if (ret)
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return NULL;
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p = pmic_get("PFUZE100");
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ret = pmic_probe(p);
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if (ret)
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return NULL;
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pmic_reg_read(p, PFUZE100_DEVICEID, ®);
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printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
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/* Set SW1AB stanby volage to 0.975V */
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pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
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reg &= ~SW1x_STBY_MASK;
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reg |= SW1x_0_975V;
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pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
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/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
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pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
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reg &= ~SW1xCONF_DVSSPEED_MASK;
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reg |= SW1xCONF_DVSSPEED_4US;
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pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
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/* Set SW1C standby voltage to 0.975V */
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pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
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reg &= ~SW1x_STBY_MASK;
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reg |= SW1x_0_975V;
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pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
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/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
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pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
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reg &= ~SW1xCONF_DVSSPEED_MASK;
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reg |= SW1xCONF_DVSSPEED_4US;
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pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
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return p;
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}
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static int pfuze_mode_init(struct pmic *p, u32 mode)
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{
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unsigned char offset, i, switch_num;
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u32 id;
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int ret;
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pmic_reg_read(p, PFUZE100_DEVICEID, &id);
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id = id & 0xf;
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if (id == 0) {
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switch_num = 6;
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offset = PFUZE100_SW1CMODE;
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} else if (id == 1) {
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switch_num = 4;
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offset = PFUZE100_SW2MODE;
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} else {
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printf("Not supported, id=%d\n", id);
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return -EINVAL;
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}
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ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
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if (ret < 0) {
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printf("Set SW1AB mode error!\n");
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return ret;
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}
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for (i = 0; i < switch_num - 1; i++) {
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ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
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if (ret < 0) {
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printf("Set switch 0x%x mode error!\n",
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offset + i * SWITCH_SIZE);
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return ret;
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}
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}
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return ret;
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}
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int power_init_board(void)
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{
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struct pmic *p;
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int ret;
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p = pfuze_init(I2C_PMIC);
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if (!p)
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return -ENODEV;
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ret = pfuze_mode_init(p, APS_PFM);
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if (ret < 0)
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return ret;
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return 0;
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}
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#ifdef CONFIG_USB_EHCI_MX6
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static iomux_v3_cfg_t const usb_otg_pads[] = {
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/* OGT1 */
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MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* OTG2 */
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MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
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};
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static void setup_iomux_usb(void)
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{
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imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
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ARRAY_SIZE(usb_otg_pads));
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}
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int board_usb_phy_mode(int port)
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{
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if (port == 1)
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return USB_INIT_HOST;
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else
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return usb_phy_mode(port);
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}
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#endif
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#ifdef CONFIG_PWM_IMX
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static int set_pwm_leds(void)
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{
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int ret;
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imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
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ARRAY_SIZE(pwm_led_pads));
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/* enable backlight PWM 2, green LED */
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ret = pwm_init(1, 0, 0);
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if (ret)
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goto error;
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/* duty cycle 200ns, period: 8000ns */
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ret = pwm_config(1, 200, 8000);
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if (ret)
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goto error;
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ret = pwm_enable(1);
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if (ret)
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goto error;
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/* enable backlight PWM 1, blue LED */
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ret = pwm_init(0, 0, 0);
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if (ret)
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goto error;
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/* duty cycle 200ns, period: 8000ns */
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ret = pwm_config(0, 200, 8000);
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if (ret)
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goto error;
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ret = pwm_enable(0);
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if (ret)
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goto error;
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/* enable backlight PWM 6, red LED */
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ret = pwm_init(5, 0, 0);
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if (ret)
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goto error;
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/* duty cycle 200ns, period: 8000ns */
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ret = pwm_config(5, 200, 8000);
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if (ret)
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goto error;
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ret = pwm_enable(5);
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error:
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return ret;
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}
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#else
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static int set_pwm_leds(void)
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{
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return 0;
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}
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#endif
|
|
|
|
#define ADCx_HC0 0x00
|
|
#define ADCx_HS 0x08
|
|
#define ADCx_HS_C0 BIT(0)
|
|
#define ADCx_R0 0x0c
|
|
#define ADCx_CFG 0x14
|
|
#define ADCx_CFG_SWMODE 0x308
|
|
#define ADCx_GC 0x18
|
|
#define ADCx_GC_CAL BIT(7)
|
|
|
|
static int read_adc(u32 *val)
|
|
{
|
|
int ret;
|
|
void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
|
|
|
|
/* use software mode */
|
|
writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
|
|
|
|
/* start auto calibration */
|
|
setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
|
|
ret = wait_for_bit("ADC", b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
|
|
if (ret)
|
|
goto adc_exit;
|
|
|
|
/* start conversion */
|
|
writel(0, b + ADCx_HC0);
|
|
|
|
/* wait for conversion */
|
|
ret = wait_for_bit("ADC", b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
|
|
if (ret)
|
|
goto adc_exit;
|
|
|
|
/* read result */
|
|
*val = readl(b + ADCx_R0);
|
|
|
|
adc_exit:
|
|
if (ret)
|
|
printf("ADC failure (ret=%i)\n", ret);
|
|
unmap_physmem(b, MAP_NOCACHE);
|
|
return ret;
|
|
}
|
|
|
|
#define VAL_UPPER 2498
|
|
#define VAL_LOWER 1550
|
|
|
|
static int set_pin_state(void)
|
|
{
|
|
u32 val;
|
|
int ret;
|
|
|
|
ret = read_adc(&val);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (val >= VAL_UPPER)
|
|
setenv("pin_state", "connected");
|
|
else if (val < VAL_UPPER && val > VAL_LOWER)
|
|
setenv("pin_state", "open");
|
|
else
|
|
setenv("pin_state", "button");
|
|
|
|
return ret;
|
|
}
|
|
|
|
int board_late_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = set_pwm_leds();
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = set_pin_state();
|
|
|
|
return ret;
|
|
}
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
setup_iomux_uart();
|
|
|
|
setup_iomux_usb();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
|
|
{USDHC4_BASE_ADDR, 0, 8},
|
|
{USDHC2_BASE_ADDR, 0, 4},
|
|
};
|
|
|
|
#define USDHC2_CD_GPIO IMX_GPIO_NR(3, 28)
|
|
|
|
int board_mmc_getcd(struct mmc *mmc)
|
|
{
|
|
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
|
|
|
if (cfg->esdhc_base == USDHC4_BASE_ADDR)
|
|
return 1;
|
|
if (cfg->esdhc_base == USDHC2_BASE_ADDR)
|
|
return !gpio_get_value(USDHC2_CD_GPIO);
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
int board_mmc_init(bd_t *bis)
|
|
{
|
|
int ret;
|
|
|
|
/*
|
|
* According to the board_mmc_init() the following map is done:
|
|
* (U-Boot device node) (Physical Port)
|
|
* mmc0 USDHC4
|
|
* mmc1 USDHC2
|
|
*/
|
|
imx_iomux_v3_setup_multiple_pads(
|
|
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
|
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
|
|
|
imx_iomux_v3_setup_multiple_pads(
|
|
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
|
|
gpio_direction_input(USDHC2_CD_GPIO);
|
|
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
|
|
|
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
|
if (ret) {
|
|
printf("Warning: failed to initialize USDHC4\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
|
|
if (ret) {
|
|
printf("Warning: failed to initialize USDHC2\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
/* Address of boot parameters */
|
|
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
|
|
|
#ifdef CONFIG_SYS_I2C_MXC
|
|
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
puts("Board: VIN|ING 2000\n");
|
|
|
|
return 0;
|
|
}
|