mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 18:59:44 +00:00
25ddd1fb0a
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
305 lines
9.4 KiB
C
305 lines
9.4 KiB
C
/*
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* (C) Copyright 2004
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* Tolunay Orkun, Nextio Inc., torkun@nextio.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
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#define CONFIG_4xx 1 /* ...member of PPC4xx family */
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#define CONFIG_CSB472 1 /* on a Cogent CSB472 board */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
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#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
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#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
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#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
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/*
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* OS Bootstrap configuration
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*
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*/
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */
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#endif
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */
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#if 1
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"setenv bootargs console=ttyS0,38400 debug " \
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"root=/dev/ram rw ramdisk_size=4096 " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
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"bootm ff800000 ff900000"
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#endif
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#if 0
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"bootp; " \
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"setenv bootargs console=ttyS0,38400 debug " \
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"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
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"bootm"
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_DNS2
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_BEDBUG
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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/*
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* Serial download configuration
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*
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*/
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* KGDB Configuration
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*
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*/
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Miscellaneous configurable options
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*
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*/
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#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* hush shell secondary prompt */
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#endif
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* watchdog configuration
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*
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*/
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* UART configuration
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*
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*/
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* use internal serial clock */
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#define CONFIG_SYS_BASE_BAUD 691200
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#define CONFIG_BAUDRATE 38400 /* Default baud rate */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
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/*
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* I2C configuration
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*
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
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#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
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#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
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/*
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* MII PHY configuration
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*
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*/
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#define CONFIG_PPC4xx_EMAC
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
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/* 32usec min. for LXT971A */
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#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
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#define CONFIG_NET_MULTI
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/*
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* RTC configuration
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*
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* Note that DS1307 RTC is limited to 100Khz I2C bus.
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*
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*/
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#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */
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/*
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* PCI stuff
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*
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*/
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#define CONFIG_PCI /* include pci support */
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
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#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
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#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
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#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
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#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
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#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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/*
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* IDE stuff
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*
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*/
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#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#undef CONFIG_IDE_RESET /* no reset for ide supported */
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/*
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* Environment configuration
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*
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */
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#undef CONFIG_ENV_IS_IN_NVRAM
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#undef CONFIG_ENV_IS_IN_EEPROM
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/*
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* General Memory organization
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*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xFF800000
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#define CONFIG_SYS_FLASH_SIZE 0x00800000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */
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#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_RAMSTART
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#endif
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#if defined(CONFIG_ENV_IS_IN_FLASH)
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#define CONFIG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */
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#define CONFIG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */
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#define CONFIG_ENV_SIZE 0x00001000 /* Size of Environment */
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#define CONFIG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */
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#endif
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/*
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* FLASH Device configuration
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*
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*/
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#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */
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#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
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#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
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#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max # of sectors on one chip */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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/*
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* On Chip Memory location/size
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*
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*/
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#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
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#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
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/*
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* Global info and initial stack
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*
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
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#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*
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* Miscellaneous board specific definitions
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*
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*/
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#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */
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#endif /* __CONFIG_H */
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