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https://github.com/AsahiLinux/u-boot
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012522fef3
Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG, MDHA, SKHA, INTC, and FlexBus structures and definitions in immap_5xxx.h to more unify modules header files. Append DSPI support for m547x_8x. SSI cleanup. Remove USB Host structure from immap_539.h. Apply changes to use FlexBus structures in mcf52x2's cpu_init.c and platform configuration files. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
139 lines
4.2 KiB
C
139 lines
4.2 KiB
C
/*
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* Edge Port Memory Map
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*
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* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __EPORT_H__
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#define __EPORT_H__
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/* Edge Port Module (EPORT) */
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typedef struct eport {
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#ifdef CONFIG_MCF547x_8x
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u16 par; /* 0x00 */
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u16 res0; /* 0x02 */
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u8 ddr; /* 0x04 */
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u8 ier; /* 0x05 */
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u16 res1; /* 0x06 */
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u8 dr; /* 0x08 */
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u8 pdr; /* 0x09 */
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u16 res2; /* 0x0A */
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u8 fr; /* 0x0C */
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u8 res3[3]; /* 0x0D */
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#else
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u16 par; /* 0x00 Pin Assignment */
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u8 ddr; /* 0x02 Data Direction */
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u8 ier; /* 0x03 Interrupt Enable */
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u8 dr; /* 0x04 Data */
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u8 pdr; /* 0x05 Pin Data */
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u8 fr; /* 0x06 Flag */
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u8 res0;
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#endif
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} eport_t;
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/* EPPAR */
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#define EPORT_PAR_EPPA1(x) (((x)&0x0003)<<2)
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#define EPORT_PAR_EPPA2(x) (((x)&0x0003)<<4)
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#define EPORT_PAR_EPPA3(x) (((x)&0x0003)<<6)
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#define EPORT_PAR_EPPA4(x) (((x)&0x0003)<<8)
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#define EPORT_PAR_EPPA5(x) (((x)&0x0003)<<10)
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#define EPORT_PAR_EPPA6(x) (((x)&0x0003)<<12)
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#define EPORT_PAR_EPPA7(x) (((x)&0x0003)<<14)
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#define EPORT_PAR_LEVEL (0)
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#define EPORT_PAR_RISING (1)
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#define EPORT_PAR_FALLING (2)
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#define EPORT_PAR_BOTH (3)
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#define EPORT_PAR_EPPA7_LEVEL (0x0000)
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#define EPORT_PAR_EPPA7_RISING (0x4000)
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#define EPORT_PAR_EPPA7_FALLING (0x8000)
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#define EPORT_PAR_EPPA7_BOTH (0xC000)
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#define EPORT_PAR_EPPA6_LEVEL (0x0000)
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#define EPORT_PAR_EPPA6_RISING (0x1000)
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#define EPORT_PAR_EPPA6_FALLING (0x2000)
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#define EPORT_PAR_EPPA6_BOTH (0x3000)
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#define EPORT_PAR_EPPA5_LEVEL (0x0000)
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#define EPORT_PAR_EPPA5_RISING (0x0400)
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#define EPORT_PAR_EPPA5_FALLING (0x0800)
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#define EPORT_PAR_EPPA5_BOTH (0x0C00)
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#define EPORT_PAR_EPPA4_LEVEL (0x0000)
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#define EPORT_PAR_EPPA4_RISING (0x0100)
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#define EPORT_PAR_EPPA4_FALLING (0x0200)
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#define EPORT_PAR_EPPA4_BOTH (0x0300)
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#define EPORT_PAR_EPPA3_LEVEL (0x0000)
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#define EPORT_PAR_EPPA3_RISING (0x0040)
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#define EPORT_PAR_EPPA3_FALLING (0x0080)
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#define EPORT_PAR_EPPA3_BOTH (0x00C0)
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#define EPORT_PAR_EPPA2_LEVEL (0x0000)
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#define EPORT_PAR_EPPA2_RISING (0x0010)
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#define EPORT_PAR_EPPA2_FALLING (0x0020)
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#define EPORT_PAR_EPPA2_BOTH (0x0030)
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#define EPORT_PAR_EPPA1_LEVEL (0x0000)
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#define EPORT_PAR_EPPA1_RISING (0x0004)
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#define EPORT_PAR_EPPA1_FALLING (0x0008)
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#define EPORT_PAR_EPPA1_BOTH (0x000C)
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/* EPDDR */
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#define EPORT_DDR_EPDD1 (0x02)
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#define EPORT_DDR_EPDD2 (0x04)
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#define EPORT_DDR_EPDD3 (0x08)
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#define EPORT_DDR_EPDD4 (0x10)
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#define EPORT_DDR_EPDD5 (0x20)
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#define EPORT_DDR_EPDD6 (0x40)
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#define EPORT_DDR_EPDD7 (0x80)
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/* EPIER */
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#define EPORT_IER_EPIE1 (0x02)
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#define EPORT_IER_EPIE2 (0x04)
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#define EPORT_IER_EPIE3 (0x08)
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#define EPORT_IER_EPIE4 (0x10)
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#define EPORT_IER_EPIE5 (0x20)
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#define EPORT_IER_EPIE6 (0x40)
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#define EPORT_IER_EPIE7 (0x80)
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/* EPDR */
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#define EPORT_DR_EPD1 (0x02)
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#define EPORT_DR_EPD2 (0x04)
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#define EPORT_DR_EPD3 (0x08)
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#define EPORT_DR_EPD4 (0x10)
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#define EPORT_DR_EPD5 (0x20)
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#define EPORT_DR_EPD6 (0x40)
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#define EPORT_DR_EPD7 (0x80)
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/* EPPDR */
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#define EPORT_PDR_EPPD1 (0x02)
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#define EPORT_PDR_EPPD2 (0x04)
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#define EPORT_PDR_EPPD3 (0x08)
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#define EPORT_PDR_EPPD4 (0x10)
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#define EPORT_PDR_EPPD5 (0x20)
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#define EPORT_PDR_EPPD6 (0x40)
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#define EPORT_PDR_EPPD7 (0x80)
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/* EPFR */
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#define EPORT_FR_EPF1 (0x02)
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#define EPORT_FR_EPF2 (0x04)
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#define EPORT_FR_EPF3 (0x08)
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#define EPORT_FR_EPF4 (0x10)
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#define EPORT_FR_EPF5 (0x20)
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#define EPORT_FR_EPF6 (0x40)
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#define EPORT_FR_EPF7 (0x80)
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#endif /* __EPORT_H__ */
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