mirror of
https://github.com/AsahiLinux/u-boot
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382bee57f1
We are now using an env_ prefix for environment functions. Rename setenv() for consistency. Also add function comments in common.h. Suggested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
1079 lines
28 KiB
C
1079 lines
28 KiB
C
/*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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*
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <linux/errno.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/video.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <i2c.h>
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#include <power/pmic.h>
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#include <power/pfuze100_pmic.h>
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#include "../common/pfuze.h"
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#include <usb.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#define I2C_PMIC 1
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#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
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#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
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#define KEY_VOL_UP IMX_GPIO_NR(1, 4)
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const enet_pads[] = {
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IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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/* AR8031 PHY Reset */
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IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static void setup_iomux_enet(void)
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{
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SETUP_IOMUX_PADS(enet_pads);
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/* Reset AR8031 PHY */
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gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
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mdelay(10);
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gpio_set_value(IMX_GPIO_NR(1, 25), 1);
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udelay(100);
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}
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
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};
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
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};
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static iomux_v3_cfg_t const usdhc4_pads[] = {
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IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const ecspi1_pads[] = {
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IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
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IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
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IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
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IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const rgb_pads[] = {
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IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const bl_pads[] = {
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IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static void enable_backlight(void)
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{
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SETUP_IOMUX_PADS(bl_pads);
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gpio_direction_output(DISP0_PWR_EN, 1);
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}
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static void enable_rgb(struct display_info_t const *dev)
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{
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SETUP_IOMUX_PADS(rgb_pads);
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enable_backlight();
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}
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static void enable_lvds(struct display_info_t const *dev)
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{
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enable_backlight();
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}
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static struct i2c_pads_info mx6q_i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
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.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
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.gp = IMX_GPIO_NR(4, 12)
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},
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.sda = {
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.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
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.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
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.gp = IMX_GPIO_NR(4, 13)
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}
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};
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static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
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.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
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.gp = IMX_GPIO_NR(4, 12)
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},
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.sda = {
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.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
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.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
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.gp = IMX_GPIO_NR(4, 13)
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}
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};
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static void setup_spi(void)
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{
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SETUP_IOMUX_PADS(ecspi1_pads);
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}
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iomux_v3_cfg_t const pcie_pads[] = {
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IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* POWER */
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IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RESET */
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};
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static void setup_pcie(void)
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{
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SETUP_IOMUX_PADS(pcie_pads);
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}
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iomux_v3_cfg_t const di0_pads[] = {
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IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */
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IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* DISP0_HSYNC */
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IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* DISP0_VSYNC */
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};
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static void setup_iomux_uart(void)
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{
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SETUP_IOMUX_PADS(uart1_pads);
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}
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg usdhc_cfg[3] = {
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{USDHC2_BASE_ADDR},
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{USDHC3_BASE_ADDR},
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{USDHC4_BASE_ADDR},
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};
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#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
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#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
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int board_mmc_get_env_dev(int devno)
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{
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return devno - 1;
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC2_BASE_ADDR:
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ret = !gpio_get_value(USDHC2_CD_GPIO);
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break;
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case USDHC3_BASE_ADDR:
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ret = !gpio_get_value(USDHC3_CD_GPIO);
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break;
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case USDHC4_BASE_ADDR:
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ret = 1; /* eMMC/uSDHC4 is always present */
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break;
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}
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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#ifndef CONFIG_SPL_BUILD
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int ret;
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int i;
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/*
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* According to the board_mmc_init() the following map is done:
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* (U-Boot device node) (Physical Port)
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* mmc0 SD2
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* mmc1 SD3
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* mmc2 eMMC
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*/
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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switch (i) {
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case 0:
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SETUP_IOMUX_PADS(usdhc2_pads);
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gpio_direction_input(USDHC2_CD_GPIO);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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break;
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case 1:
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SETUP_IOMUX_PADS(usdhc3_pads);
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gpio_direction_input(USDHC3_CD_GPIO);
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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break;
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case 2:
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SETUP_IOMUX_PADS(usdhc4_pads);
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usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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break;
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default:
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printf("Warning: you configured more USDHC controllers"
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"(%d) then supported by the board (%d)\n",
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i + 1, CONFIG_SYS_FSL_USDHC_NUM);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
#else
|
|
struct src *psrc = (struct src *)SRC_BASE_ADDR;
|
|
unsigned reg = readl(&psrc->sbmr1) >> 11;
|
|
/*
|
|
* Upon reading BOOT_CFG register the following map is done:
|
|
* Bit 11 and 12 of BOOT_CFG register can determine the current
|
|
* mmc port
|
|
* 0x1 SD1
|
|
* 0x2 SD2
|
|
* 0x3 SD4
|
|
*/
|
|
|
|
switch (reg & 0x3) {
|
|
case 0x1:
|
|
SETUP_IOMUX_PADS(usdhc2_pads);
|
|
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
|
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
|
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
|
|
break;
|
|
case 0x2:
|
|
SETUP_IOMUX_PADS(usdhc3_pads);
|
|
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
|
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
|
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
|
|
break;
|
|
case 0x3:
|
|
SETUP_IOMUX_PADS(usdhc4_pads);
|
|
usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
|
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
|
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
|
|
break;
|
|
}
|
|
|
|
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
static int ar8031_phy_fixup(struct phy_device *phydev)
|
|
{
|
|
unsigned short val;
|
|
|
|
/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
|
|
|
|
val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
|
|
val &= 0xffe3;
|
|
val |= 0x18;
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
|
|
|
|
/* introduce tx clock delay */
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
|
|
val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
|
|
val |= 0x0100;
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_phy_config(struct phy_device *phydev)
|
|
{
|
|
ar8031_phy_fixup(phydev);
|
|
|
|
if (phydev->drv->config)
|
|
phydev->drv->config(phydev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_VIDEO_IPUV3)
|
|
static void disable_lvds(struct display_info_t const *dev)
|
|
{
|
|
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
|
|
|
int reg = readl(&iomux->gpr[2]);
|
|
|
|
reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
|
|
IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
|
|
|
|
writel(reg, &iomux->gpr[2]);
|
|
}
|
|
|
|
static void do_enable_hdmi(struct display_info_t const *dev)
|
|
{
|
|
disable_lvds(dev);
|
|
imx_enable_hdmi_phy();
|
|
}
|
|
|
|
struct display_info_t const displays[] = {{
|
|
.bus = -1,
|
|
.addr = 0,
|
|
.pixfmt = IPU_PIX_FMT_RGB666,
|
|
.detect = NULL,
|
|
.enable = enable_lvds,
|
|
.mode = {
|
|
.name = "Hannstar-XGA",
|
|
.refresh = 60,
|
|
.xres = 1024,
|
|
.yres = 768,
|
|
.pixclock = 15384,
|
|
.left_margin = 160,
|
|
.right_margin = 24,
|
|
.upper_margin = 29,
|
|
.lower_margin = 3,
|
|
.hsync_len = 136,
|
|
.vsync_len = 6,
|
|
.sync = FB_SYNC_EXT,
|
|
.vmode = FB_VMODE_NONINTERLACED
|
|
} }, {
|
|
.bus = -1,
|
|
.addr = 0,
|
|
.pixfmt = IPU_PIX_FMT_RGB24,
|
|
.detect = detect_hdmi,
|
|
.enable = do_enable_hdmi,
|
|
.mode = {
|
|
.name = "HDMI",
|
|
.refresh = 60,
|
|
.xres = 1024,
|
|
.yres = 768,
|
|
.pixclock = 15384,
|
|
.left_margin = 160,
|
|
.right_margin = 24,
|
|
.upper_margin = 29,
|
|
.lower_margin = 3,
|
|
.hsync_len = 136,
|
|
.vsync_len = 6,
|
|
.sync = FB_SYNC_EXT,
|
|
.vmode = FB_VMODE_NONINTERLACED
|
|
} }, {
|
|
.bus = 0,
|
|
.addr = 0,
|
|
.pixfmt = IPU_PIX_FMT_RGB24,
|
|
.detect = NULL,
|
|
.enable = enable_rgb,
|
|
.mode = {
|
|
.name = "SEIKO-WVGA",
|
|
.refresh = 60,
|
|
.xres = 800,
|
|
.yres = 480,
|
|
.pixclock = 29850,
|
|
.left_margin = 89,
|
|
.right_margin = 164,
|
|
.upper_margin = 23,
|
|
.lower_margin = 10,
|
|
.hsync_len = 10,
|
|
.vsync_len = 10,
|
|
.sync = 0,
|
|
.vmode = FB_VMODE_NONINTERLACED
|
|
} } };
|
|
size_t display_count = ARRAY_SIZE(displays);
|
|
|
|
static void setup_display(void)
|
|
{
|
|
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
|
int reg;
|
|
|
|
/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
|
|
SETUP_IOMUX_PADS(di0_pads);
|
|
|
|
enable_ipu_clock();
|
|
imx_setup_hdmi();
|
|
|
|
/* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
|
|
reg = readl(&mxc_ccm->CCGR3);
|
|
reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
|
|
writel(reg, &mxc_ccm->CCGR3);
|
|
|
|
/* set LDB0, LDB1 clk select to 011/011 */
|
|
reg = readl(&mxc_ccm->cs2cdr);
|
|
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
|
|
| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
|
|
reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
|
|
| (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
|
|
writel(reg, &mxc_ccm->cs2cdr);
|
|
|
|
reg = readl(&mxc_ccm->cscmr2);
|
|
reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
|
|
writel(reg, &mxc_ccm->cscmr2);
|
|
|
|
reg = readl(&mxc_ccm->chsccdr);
|
|
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
|
|
<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
|
|
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
|
|
<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
|
|
writel(reg, &mxc_ccm->chsccdr);
|
|
|
|
reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
|
|
| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
|
|
| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
|
|
| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
|
|
| IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
|
|
| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
|
|
| IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
|
|
| IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
|
|
| IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
|
|
writel(reg, &iomux->gpr[2]);
|
|
|
|
reg = readl(&iomux->gpr[3]);
|
|
reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
|
|
| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
|
|
| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
|
|
<< IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
|
|
writel(reg, &iomux->gpr[3]);
|
|
}
|
|
#endif /* CONFIG_VIDEO_IPUV3 */
|
|
|
|
/*
|
|
* Do not overwrite the console
|
|
* Use always serial for U-Boot console
|
|
*/
|
|
int overwrite_console(void)
|
|
{
|
|
return 1;
|
|
}
|
|
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
setup_iomux_enet();
|
|
setup_pcie();
|
|
|
|
return cpu_eth_init(bis);
|
|
}
|
|
|
|
#ifdef CONFIG_USB_EHCI_MX6
|
|
#define USB_OTHERREGS_OFFSET 0x800
|
|
#define UCTRL_PWR_POL (1 << 9)
|
|
|
|
static iomux_v3_cfg_t const usb_otg_pads[] = {
|
|
IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
};
|
|
|
|
static iomux_v3_cfg_t const usb_hc1_pads[] = {
|
|
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
};
|
|
|
|
static void setup_usb(void)
|
|
{
|
|
SETUP_IOMUX_PADS(usb_otg_pads);
|
|
|
|
/*
|
|
* set daisy chain for otg_pin_id on 6q.
|
|
* for 6dl, this bit is reserved
|
|
*/
|
|
imx_iomux_set_gpr_register(1, 13, 1, 0);
|
|
|
|
SETUP_IOMUX_PADS(usb_hc1_pads);
|
|
}
|
|
|
|
int board_ehci_hcd_init(int port)
|
|
{
|
|
u32 *usbnc_usb_ctrl;
|
|
|
|
if (port > 1)
|
|
return -EINVAL;
|
|
|
|
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
|
|
port * 4);
|
|
|
|
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_ehci_power(int port, int on)
|
|
{
|
|
switch (port) {
|
|
case 0:
|
|
break;
|
|
case 1:
|
|
if (on)
|
|
gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
|
|
else
|
|
gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
|
|
break;
|
|
default:
|
|
printf("MXC USB port %d not yet supported\n", port);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
setup_iomux_uart();
|
|
#if defined(CONFIG_VIDEO_IPUV3)
|
|
setup_display();
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
/* address of boot parameters */
|
|
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
|
|
|
#ifdef CONFIG_MXC_SPI
|
|
setup_spi();
|
|
#endif
|
|
if (is_mx6dq() || is_mx6dqp())
|
|
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
|
|
else
|
|
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
|
|
#ifdef CONFIG_USB_EHCI_MX6
|
|
setup_usb();
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int power_init_board(void)
|
|
{
|
|
struct pmic *p;
|
|
unsigned int reg;
|
|
int ret;
|
|
|
|
p = pfuze_common_init(I2C_PMIC);
|
|
if (!p)
|
|
return -ENODEV;
|
|
|
|
ret = pfuze_mode_init(p, APS_PFM);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Increase VGEN3 from 2.5 to 2.8V */
|
|
pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
|
|
reg &= ~LDO_VOL_MASK;
|
|
reg |= LDOB_2_80V;
|
|
pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
|
|
|
|
/* Increase VGEN5 from 2.8 to 3V */
|
|
pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
|
|
reg &= ~LDO_VOL_MASK;
|
|
reg |= LDOB_3_00V;
|
|
pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_MXC_SPI
|
|
int board_spi_cs_gpio(unsigned bus, unsigned cs)
|
|
{
|
|
return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_CMD_BMODE
|
|
static const struct boot_mode board_boot_modes[] = {
|
|
/* 4 bit bus width */
|
|
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
|
|
{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
|
|
/* 8 bit bus width */
|
|
{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
|
|
{NULL, 0},
|
|
};
|
|
#endif
|
|
|
|
int board_late_init(void)
|
|
{
|
|
#ifdef CONFIG_CMD_BMODE
|
|
add_board_boot_modes(board_boot_modes);
|
|
#endif
|
|
|
|
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
|
env_set("board_name", "SABRESD");
|
|
|
|
if (is_mx6dqp())
|
|
env_set("board_rev", "MX6QP");
|
|
else if (is_mx6dq())
|
|
env_set("board_rev", "MX6Q");
|
|
else if (is_mx6sdl())
|
|
env_set("board_rev", "MX6DL");
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
puts("Board: MX6-SabreSD\n");
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_SPL_BUILD
|
|
#include <asm/arch/mx6-ddr.h>
|
|
#include <spl.h>
|
|
#include <libfdt.h>
|
|
|
|
#ifdef CONFIG_SPL_OS_BOOT
|
|
int spl_start_uboot(void)
|
|
{
|
|
gpio_direction_input(KEY_VOL_UP);
|
|
|
|
/* Only enter in Falcon mode if KEY_VOL_UP is pressed */
|
|
return gpio_get_value(KEY_VOL_UP);
|
|
}
|
|
#endif
|
|
|
|
static void ccgr_init(void)
|
|
{
|
|
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
|
writel(0x00C03F3F, &ccm->CCGR0);
|
|
writel(0x0030FC03, &ccm->CCGR1);
|
|
writel(0x0FFFC000, &ccm->CCGR2);
|
|
writel(0x3FF00000, &ccm->CCGR3);
|
|
writel(0x00FFF300, &ccm->CCGR4);
|
|
writel(0x0F0000C3, &ccm->CCGR5);
|
|
writel(0x000003FF, &ccm->CCGR6);
|
|
}
|
|
|
|
static void gpr_init(void)
|
|
{
|
|
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
|
|
|
/* enable AXI cache for VDOA/VPU/IPU */
|
|
writel(0xF00000CF, &iomux->gpr[4]);
|
|
if (is_mx6dqp()) {
|
|
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
|
|
writel(0x007F007F, &iomux->gpr[6]);
|
|
writel(0x007F007F, &iomux->gpr[7]);
|
|
} else {
|
|
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
|
writel(0x007F007F, &iomux->gpr[6]);
|
|
writel(0x007F007F, &iomux->gpr[7]);
|
|
}
|
|
}
|
|
|
|
static int mx6q_dcd_table[] = {
|
|
0x020e0798, 0x000C0000,
|
|
0x020e0758, 0x00000000,
|
|
0x020e0588, 0x00000030,
|
|
0x020e0594, 0x00000030,
|
|
0x020e056c, 0x00000030,
|
|
0x020e0578, 0x00000030,
|
|
0x020e074c, 0x00000030,
|
|
0x020e057c, 0x00000030,
|
|
0x020e058c, 0x00000000,
|
|
0x020e059c, 0x00000030,
|
|
0x020e05a0, 0x00000030,
|
|
0x020e078c, 0x00000030,
|
|
0x020e0750, 0x00020000,
|
|
0x020e05a8, 0x00000030,
|
|
0x020e05b0, 0x00000030,
|
|
0x020e0524, 0x00000030,
|
|
0x020e051c, 0x00000030,
|
|
0x020e0518, 0x00000030,
|
|
0x020e050c, 0x00000030,
|
|
0x020e05b8, 0x00000030,
|
|
0x020e05c0, 0x00000030,
|
|
0x020e0774, 0x00020000,
|
|
0x020e0784, 0x00000030,
|
|
0x020e0788, 0x00000030,
|
|
0x020e0794, 0x00000030,
|
|
0x020e079c, 0x00000030,
|
|
0x020e07a0, 0x00000030,
|
|
0x020e07a4, 0x00000030,
|
|
0x020e07a8, 0x00000030,
|
|
0x020e0748, 0x00000030,
|
|
0x020e05ac, 0x00000030,
|
|
0x020e05b4, 0x00000030,
|
|
0x020e0528, 0x00000030,
|
|
0x020e0520, 0x00000030,
|
|
0x020e0514, 0x00000030,
|
|
0x020e0510, 0x00000030,
|
|
0x020e05bc, 0x00000030,
|
|
0x020e05c4, 0x00000030,
|
|
0x021b0800, 0xa1390003,
|
|
0x021b080c, 0x001F001F,
|
|
0x021b0810, 0x001F001F,
|
|
0x021b480c, 0x001F001F,
|
|
0x021b4810, 0x001F001F,
|
|
0x021b083c, 0x43270338,
|
|
0x021b0840, 0x03200314,
|
|
0x021b483c, 0x431A032F,
|
|
0x021b4840, 0x03200263,
|
|
0x021b0848, 0x4B434748,
|
|
0x021b4848, 0x4445404C,
|
|
0x021b0850, 0x38444542,
|
|
0x021b4850, 0x4935493A,
|
|
0x021b081c, 0x33333333,
|
|
0x021b0820, 0x33333333,
|
|
0x021b0824, 0x33333333,
|
|
0x021b0828, 0x33333333,
|
|
0x021b481c, 0x33333333,
|
|
0x021b4820, 0x33333333,
|
|
0x021b4824, 0x33333333,
|
|
0x021b4828, 0x33333333,
|
|
0x021b08b8, 0x00000800,
|
|
0x021b48b8, 0x00000800,
|
|
0x021b0004, 0x00020036,
|
|
0x021b0008, 0x09444040,
|
|
0x021b000c, 0x555A7975,
|
|
0x021b0010, 0xFF538F64,
|
|
0x021b0014, 0x01FF00DB,
|
|
0x021b0018, 0x00001740,
|
|
0x021b001c, 0x00008000,
|
|
0x021b002c, 0x000026d2,
|
|
0x021b0030, 0x005A1023,
|
|
0x021b0040, 0x00000027,
|
|
0x021b0000, 0x831A0000,
|
|
0x021b001c, 0x04088032,
|
|
0x021b001c, 0x00008033,
|
|
0x021b001c, 0x00048031,
|
|
0x021b001c, 0x09408030,
|
|
0x021b001c, 0x04008040,
|
|
0x021b0020, 0x00005800,
|
|
0x021b0818, 0x00011117,
|
|
0x021b4818, 0x00011117,
|
|
0x021b0004, 0x00025576,
|
|
0x021b0404, 0x00011006,
|
|
0x021b001c, 0x00000000,
|
|
};
|
|
|
|
static int mx6qp_dcd_table[] = {
|
|
0x020e0798, 0x000c0000,
|
|
0x020e0758, 0x00000000,
|
|
0x020e0588, 0x00000030,
|
|
0x020e0594, 0x00000030,
|
|
0x020e056c, 0x00000030,
|
|
0x020e0578, 0x00000030,
|
|
0x020e074c, 0x00000030,
|
|
0x020e057c, 0x00000030,
|
|
0x020e058c, 0x00000000,
|
|
0x020e059c, 0x00000030,
|
|
0x020e05a0, 0x00000030,
|
|
0x020e078c, 0x00000030,
|
|
0x020e0750, 0x00020000,
|
|
0x020e05a8, 0x00000030,
|
|
0x020e05b0, 0x00000030,
|
|
0x020e0524, 0x00000030,
|
|
0x020e051c, 0x00000030,
|
|
0x020e0518, 0x00000030,
|
|
0x020e050c, 0x00000030,
|
|
0x020e05b8, 0x00000030,
|
|
0x020e05c0, 0x00000030,
|
|
0x020e0774, 0x00020000,
|
|
0x020e0784, 0x00000030,
|
|
0x020e0788, 0x00000030,
|
|
0x020e0794, 0x00000030,
|
|
0x020e079c, 0x00000030,
|
|
0x020e07a0, 0x00000030,
|
|
0x020e07a4, 0x00000030,
|
|
0x020e07a8, 0x00000030,
|
|
0x020e0748, 0x00000030,
|
|
0x020e05ac, 0x00000030,
|
|
0x020e05b4, 0x00000030,
|
|
0x020e0528, 0x00000030,
|
|
0x020e0520, 0x00000030,
|
|
0x020e0514, 0x00000030,
|
|
0x020e0510, 0x00000030,
|
|
0x020e05bc, 0x00000030,
|
|
0x020e05c4, 0x00000030,
|
|
0x021b0800, 0xa1390003,
|
|
0x021b080c, 0x001b001e,
|
|
0x021b0810, 0x002e0029,
|
|
0x021b480c, 0x001b002a,
|
|
0x021b4810, 0x0019002c,
|
|
0x021b083c, 0x43240334,
|
|
0x021b0840, 0x0324031a,
|
|
0x021b483c, 0x43340344,
|
|
0x021b4840, 0x03280276,
|
|
0x021b0848, 0x44383A3E,
|
|
0x021b4848, 0x3C3C3846,
|
|
0x021b0850, 0x2e303230,
|
|
0x021b4850, 0x38283E34,
|
|
0x021b081c, 0x33333333,
|
|
0x021b0820, 0x33333333,
|
|
0x021b0824, 0x33333333,
|
|
0x021b0828, 0x33333333,
|
|
0x021b481c, 0x33333333,
|
|
0x021b4820, 0x33333333,
|
|
0x021b4824, 0x33333333,
|
|
0x021b4828, 0x33333333,
|
|
0x021b08c0, 0x24912249,
|
|
0x021b48c0, 0x24914289,
|
|
0x021b08b8, 0x00000800,
|
|
0x021b48b8, 0x00000800,
|
|
0x021b0004, 0x00020036,
|
|
0x021b0008, 0x24444040,
|
|
0x021b000c, 0x555A7955,
|
|
0x021b0010, 0xFF320F64,
|
|
0x021b0014, 0x01ff00db,
|
|
0x021b0018, 0x00001740,
|
|
0x021b001c, 0x00008000,
|
|
0x021b002c, 0x000026d2,
|
|
0x021b0030, 0x005A1023,
|
|
0x021b0040, 0x00000027,
|
|
0x021b0400, 0x14420000,
|
|
0x021b0000, 0x831A0000,
|
|
0x021b0890, 0x00400C58,
|
|
0x00bb0008, 0x00000000,
|
|
0x00bb000c, 0x2891E41A,
|
|
0x00bb0038, 0x00000564,
|
|
0x00bb0014, 0x00000040,
|
|
0x00bb0028, 0x00000020,
|
|
0x00bb002c, 0x00000020,
|
|
0x021b001c, 0x04088032,
|
|
0x021b001c, 0x00008033,
|
|
0x021b001c, 0x00048031,
|
|
0x021b001c, 0x09408030,
|
|
0x021b001c, 0x04008040,
|
|
0x021b0020, 0x00005800,
|
|
0x021b0818, 0x00011117,
|
|
0x021b4818, 0x00011117,
|
|
0x021b0004, 0x00025576,
|
|
0x021b0404, 0x00011006,
|
|
0x021b001c, 0x00000000,
|
|
};
|
|
|
|
static int mx6dl_dcd_table[] = {
|
|
0x020e0774, 0x000C0000,
|
|
0x020e0754, 0x00000000,
|
|
0x020e04ac, 0x00000030,
|
|
0x020e04b0, 0x00000030,
|
|
0x020e0464, 0x00000030,
|
|
0x020e0490, 0x00000030,
|
|
0x020e074c, 0x00000030,
|
|
0x020e0494, 0x00000030,
|
|
0x020e04a0, 0x00000000,
|
|
0x020e04b4, 0x00000030,
|
|
0x020e04b8, 0x00000030,
|
|
0x020e076c, 0x00000030,
|
|
0x020e0750, 0x00020000,
|
|
0x020e04bc, 0x00000030,
|
|
0x020e04c0, 0x00000030,
|
|
0x020e04c4, 0x00000030,
|
|
0x020e04c8, 0x00000030,
|
|
0x020e04cc, 0x00000030,
|
|
0x020e04d0, 0x00000030,
|
|
0x020e04d4, 0x00000030,
|
|
0x020e04d8, 0x00000030,
|
|
0x020e0760, 0x00020000,
|
|
0x020e0764, 0x00000030,
|
|
0x020e0770, 0x00000030,
|
|
0x020e0778, 0x00000030,
|
|
0x020e077c, 0x00000030,
|
|
0x020e0780, 0x00000030,
|
|
0x020e0784, 0x00000030,
|
|
0x020e078c, 0x00000030,
|
|
0x020e0748, 0x00000030,
|
|
0x020e0470, 0x00000030,
|
|
0x020e0474, 0x00000030,
|
|
0x020e0478, 0x00000030,
|
|
0x020e047c, 0x00000030,
|
|
0x020e0480, 0x00000030,
|
|
0x020e0484, 0x00000030,
|
|
0x020e0488, 0x00000030,
|
|
0x020e048c, 0x00000030,
|
|
0x021b0800, 0xa1390003,
|
|
0x021b080c, 0x001F001F,
|
|
0x021b0810, 0x001F001F,
|
|
0x021b480c, 0x001F001F,
|
|
0x021b4810, 0x001F001F,
|
|
0x021b083c, 0x4220021F,
|
|
0x021b0840, 0x0207017E,
|
|
0x021b483c, 0x4201020C,
|
|
0x021b4840, 0x01660172,
|
|
0x021b0848, 0x4A4D4E4D,
|
|
0x021b4848, 0x4A4F5049,
|
|
0x021b0850, 0x3F3C3D31,
|
|
0x021b4850, 0x3238372B,
|
|
0x021b081c, 0x33333333,
|
|
0x021b0820, 0x33333333,
|
|
0x021b0824, 0x33333333,
|
|
0x021b0828, 0x33333333,
|
|
0x021b481c, 0x33333333,
|
|
0x021b4820, 0x33333333,
|
|
0x021b4824, 0x33333333,
|
|
0x021b4828, 0x33333333,
|
|
0x021b08b8, 0x00000800,
|
|
0x021b48b8, 0x00000800,
|
|
0x021b0004, 0x0002002D,
|
|
0x021b0008, 0x00333030,
|
|
0x021b000c, 0x3F435313,
|
|
0x021b0010, 0xB66E8B63,
|
|
0x021b0014, 0x01FF00DB,
|
|
0x021b0018, 0x00001740,
|
|
0x021b001c, 0x00008000,
|
|
0x021b002c, 0x000026d2,
|
|
0x021b0030, 0x00431023,
|
|
0x021b0040, 0x00000027,
|
|
0x021b0000, 0x831A0000,
|
|
0x021b001c, 0x04008032,
|
|
0x021b001c, 0x00008033,
|
|
0x021b001c, 0x00048031,
|
|
0x021b001c, 0x05208030,
|
|
0x021b001c, 0x04008040,
|
|
0x021b0020, 0x00005800,
|
|
0x021b0818, 0x00011117,
|
|
0x021b4818, 0x00011117,
|
|
0x021b0004, 0x0002556D,
|
|
0x021b0404, 0x00011006,
|
|
0x021b001c, 0x00000000,
|
|
};
|
|
|
|
static void ddr_init(int *table, int size)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < size / 2 ; i++)
|
|
writel(table[2 * i + 1], table[2 * i]);
|
|
}
|
|
|
|
static void spl_dram_init(void)
|
|
{
|
|
if (is_mx6dq())
|
|
ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
|
|
else if (is_mx6dqp())
|
|
ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
|
|
else if (is_mx6sdl())
|
|
ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
|
|
}
|
|
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
/* DDR initialization */
|
|
spl_dram_init();
|
|
|
|
/* setup AIPS and disable watchdog */
|
|
arch_cpu_init();
|
|
|
|
ccgr_init();
|
|
gpr_init();
|
|
|
|
/* iomux and setup of i2c */
|
|
board_early_init_f();
|
|
|
|
/* setup GP timer */
|
|
timer_init();
|
|
|
|
/* UART clocks enabled and gd valid - init serial console */
|
|
preloader_console_init();
|
|
|
|
/* Clear the BSS. */
|
|
memset(__bss_start, 0, __bss_end - __bss_start);
|
|
|
|
/* load/boot image from boot device */
|
|
board_init_r(NULL, 0);
|
|
}
|
|
#endif
|