mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-29 08:01:08 +00:00
dcf2cee77f
The driver is based on the Versaclock driver from the Linux code, but due differences in the clock API between them, some pieces had to be changed. This driver creates a mux, pfd, pll, and a series of fod ouputs. Rate Usecnt Name ------------------------------------------ 25000000 0 `-- x304-clock 25000000 0 `-- clock-controller@6a.mux 25000000 0 |-- clock-controller@6a.pfd 2800000000 0 | `-- clock-controller@6a.pll 33333333 0 | |-- clock-controller@6a.fod0 33333333 0 | | `-- clock-controller@6a.out1 33333333 0 | |-- clock-controller@6a.fod1 33333333 0 | | `-- clock-controller@6a.out2 50000000 0 | |-- clock-controller@6a.fod2 50000000 0 | | `-- clock-controller@6a.out3 125000000 0 | `-- clock-controller@6a.fod3 125000000 0 | `-- clock-controller@6a.out4 25000000 0 `-- clock-controller@6a.out0_sel_i2cb A translation function is added so the references to <&versaclock X> get routed to the corresponding clock-controller@6a.outX. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
55 lines
2 KiB
Makefile
55 lines
2 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0+
|
|
#
|
|
# Copyright (c) 2015 Google, Inc
|
|
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
#
|
|
|
|
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
|
|
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
|
|
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
|
|
obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o
|
|
obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o
|
|
obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o
|
|
|
|
obj-y += analogbits/
|
|
obj-y += imx/
|
|
obj-y += tegra/
|
|
obj-y += ti/
|
|
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
|
|
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
|
|
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
|
|
obj-$(CONFIG_ARCH_MESON) += meson/
|
|
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
|
|
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
|
|
obj-$(CONFIG_CLK_AT91) += at91/
|
|
obj-$(CONFIG_CLK_MVEBU) += mvebu/
|
|
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
|
|
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
|
|
obj-$(CONFIG_CLK_EXYNOS) += exynos/
|
|
obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
|
|
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
|
|
obj-$(CONFIG_CLK_K210) += clk_kendryte.o
|
|
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
|
|
obj-$(CONFIG_CLK_MPFS) += microchip/
|
|
obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
|
|
obj-$(CONFIG_CLK_OWL) += owl/
|
|
obj-$(CONFIG_CLK_RENESAS) += renesas/
|
|
obj-$(CONFIG_CLK_SCMI) += clk_scmi.o
|
|
obj-$(CONFIG_CLK_SIFIVE) += sifive/
|
|
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
|
|
obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
|
|
obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
|
|
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
|
|
obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
|
|
obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
|
|
obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
|
|
obj-$(CONFIG_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
|
|
obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
|
|
obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
|
|
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
|
|
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
|
|
obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
|
|
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
|
|
obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
|
|
obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
|
|
obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
|