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https://github.com/AsahiLinux/u-boot
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662f05fcb6
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap specification does not include the Critical Delay Difference (CDD) to properly define the required rank-to-rank read command spacing after executing PHY training firmware. Following the errata workaround, at the end of data training, we get all CDD values through the MessageBlock, then re-configure the DDRC timing of WWT/WRT/RRT/RWT with comparing MAX CDD values. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
128 lines
3.2 KiB
C
128 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2022 NXP
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*/
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#ifndef __ASM_ARCH_IMX8M_DDR_H
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#define __ASM_ARCH_IMX8M_DDR_H
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#include <asm/io.h>
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#include <asm/types.h>
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#define DDR_CTL_BASE 0x4E300000
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#define DDR_PHY_BASE 0x4E100000
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#define DDRMIX_BLK_CTRL_BASE 0x4E010000
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#define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24)
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#define REG_DDR_TIMING_CFG_0 (DDR_CTL_BASE + 0x104)
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#define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110)
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#define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160)
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#define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48)
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#define SRC_BASE_ADDR (0x44460000)
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#define SRC_DPHY_BASE_ADDR (SRC_BASE_ADDR + 0x1400)
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#define REG_SRC_DPHY_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x20)
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#define REG_SRC_DPHY_SINGLE_RESET_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x24)
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#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (DDR_PHY_BASE + ((X) * 0x2000000))
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#define DDRPHY_MEM(X) (DDR_PHY_BASE + ((X) * 0x2000000) + 0x50000)
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/* PHY State */
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enum pstate {
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PS0,
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PS1,
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PS2,
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PS3,
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};
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enum msg_response {
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TRAIN_SUCCESS = 0x7,
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TRAIN_STREAM_START = 0x8,
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TRAIN_FAIL = 0xff,
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};
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/* user data type */
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enum fw_type {
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FW_1D_IMAGE,
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FW_2D_IMAGE,
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};
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struct dram_cfg_param {
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unsigned int reg;
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unsigned int val;
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};
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struct dram_fsp_msg {
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unsigned int drate;
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enum fw_type fw_type;
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struct dram_cfg_param *fsp_cfg;
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unsigned int fsp_cfg_num;
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};
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struct dram_timing_info {
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/* umctl2 config */
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struct dram_cfg_param *ddrc_cfg;
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unsigned int ddrc_cfg_num;
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/* ddrphy config */
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struct dram_cfg_param *ddrphy_cfg;
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unsigned int ddrphy_cfg_num;
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/* ddr fsp train info */
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struct dram_fsp_msg *fsp_msg;
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unsigned int fsp_msg_num;
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/* ddr phy trained CSR */
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struct dram_cfg_param *ddrphy_trained_csr;
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unsigned int ddrphy_trained_csr_num;
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/* ddr phy PIE */
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struct dram_cfg_param *ddrphy_pie;
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unsigned int ddrphy_pie_num;
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/* initialized drate table */
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unsigned int fsp_table[4];
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};
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extern struct dram_timing_info dram_timing;
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void ddr_load_train_firmware(enum fw_type type);
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int ddr_init(struct dram_timing_info *timing_info);
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int ddr_cfg_phy(struct dram_timing_info *timing_info);
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void load_lpddr4_phy_pie(void);
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void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
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void dram_config_save(struct dram_timing_info *info, unsigned long base);
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void board_dram_ecc_scrub(void);
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void ddrc_inline_ecc_scrub(unsigned int start_address,
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unsigned int range_address);
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void ddrc_inline_ecc_scrub_end(unsigned int start_address,
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unsigned int range_address);
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/* utils function for ddr phy training */
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int wait_ddrphy_training_complete(void);
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void ddrphy_init_set_dfi_clk(unsigned int drate);
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void ddrphy_init_read_msg_block(enum fw_type type);
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void get_trained_CDD(unsigned int fsp);
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ulong ddrphy_addr_remap(u32 paddr_apb_from_ctlr);
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static inline void reg32_write(unsigned long addr, u32 val)
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{
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writel(val, addr);
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}
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static inline u32 reg32_read(unsigned long addr)
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{
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return readl(addr);
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}
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static inline void reg32setbit(unsigned long addr, u32 bit)
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{
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setbits_le32(addr, (1 << bit));
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}
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#define dwc_ddrphy_apb_wr(addr, data) \
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reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr), data)
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#define dwc_ddrphy_apb_rd(addr) \
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reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))
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extern struct dram_cfg_param ddrphy_trained_csr[];
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extern u32 ddrphy_trained_csr_num;
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#endif
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